• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.10
• /
• pp.1606-1616
• /
• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.227-234
• /
• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• Proceedings of the KIEE Conference
• /
• 1989.07a
• /
• pp.707-711
• /
• 1989

This system exchange half-duplex serial data at 1200 baud by FSK modulating a carrier frequency at 200KHz over the 110V A.C. power line. Transmitter output voltage to A.C. line is 4V p-p and line sensitivity is selected 2.54mV because CISPR Noise limitation is $66dB{\mu}V$ at 150 ${\sim}$ 500KHz. The designed and realized system has abtained system margin of 58 dB and probability of error, Pe = $1.78{\times}10^{-7}$ was obtained

• Proceedings of the KIEE Conference
• /
• 1999.07f
• /
• pp.2682-2684
• /
• 1999

This paper presents design and stability analysis of the constant frequency Flyback type converter using average current-mode control. The average current-mode control has been recently reported, and superior characteristics over a peak current-mode control such as a good tracking performance of an average current, no slope compensation and noise immunity. By the improvement of PM(Phase Margin) obt from applying the compensator in the current loop, the stability of designed flyback convert more improved. The validity of designed convert confirmed by simulation and experimental result

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.1
• /
• pp.15-24
• /
• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

• Journal of Astronomy and Space Sciences
• /
• v.17 no.2
• /
• pp.257-266
• /
• 2000

A satellite RF communication link is analyzed based on a simple fundamental equations by systematic approach in this paper. The number of variables related to a design and analysis of satellite RF link is often a dozen or more, thus it is a tedious and time-consuming task. With the given input data, the important parameters are calculated step by step and three communication characteristics such as communication channel capacity, carrier-to-noise ratio(CNR) at the satellite and ground station are analyzed. It gives very useful information to the system engineers for designing and analyzing the overall satellite communication system in the conceptual design phase.

• Journal of the Korea Safety Management & Science
• /
• v.2 no.3
• /
• pp.27-36
• /
• 2000

The Robust Design method uses a mathematical tool called orthogonal arrays to study a large number of decision variables with a small number of experiments. It also uses a new measure of quality, called signal-to-noise (S/N) ratio, to predict the quality from the customer's perspective. Thus, the most economical product and process design from both manufacturing and customers' viewpoints can be accomplished at the smallest, affordable development cost. Many companies, big and small, high-tech and low-tech, have found the Robust Design method valuable in making high-quality products available to customers at a low competitive price while still maintaining an acceptable profit margin. A study to analyze and solve problems of a biochemical process experiment has presented in this paper. We have taken Taguchi's parameter design approach, specifically orthogonal array, and determined the optimal levels of the selected variables through analysis of the experimental results using S/N ratio.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.54.1-54.1
• /
• 2012

Recent significant development of organic electronics is worthy of notice for its practical application as well as fundamental understandings. Complementary-like logic circuit is a key factor to realize actual operating organic electronic devices since its advantages of low power dissipation, good noise margin and stable operations. In this reason, studies on ambipolar properties of organic materials which can act as either n-type or p-type are getting more attentions. Performances of ambipolar transistors vary a lot along its molecular structures and film properties. When properly fabricated, balanced hole and electron mobilities over 1 cm2/Vs were observed recently. Study of charge transport in ambipolar organic transistors to understand this high performance was carried out through charge modulation spectroscopy.

• Journal of the Korea Safety Management & Science
• /
• v.13 no.1
• /
• pp.203-209
• /
• 2011

This study develops three new models that are practically applicable to three stages of Taguchi's robust design, which includes system design, parameter design and tolerance design. In system design, the Multiple Loss Function Analysis(MLFA) and Overall Loss Index(OLI) which reflect upon weight of characteristics and importance of specification are developed. Moreover parameter design presents Process Capability Index(PCI), $C_{PUK}$ and $C_{PLK}$, in order to segregate Signal-To-Noise Ratio(SNR) into accuracy and precision for an evaluation of relative comparison. In addition, tolerance design presents the new model of allowance computation for assembled product which is primarily derived from safety margin(SM) considering functional limit and specification. The guideline of those three new models, which include systematic charts and applicable illustrations, offers convenience for practitioners in the field. Hence, the practical applications could be made with the steps of robust designs such as system design, parameter design and specification allowance design.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.479-482
• /
• 1993

A fully balanced differential amplifier can achieve high-gain wide-bandwidth characteristics. And also, Offset PSRR, CMRR and Noise performance of that are excellent, but these merits can be achieved only when the architecture holds fully balanced. Commonly, the fully balanced differential amplifier has a common mode feedback(CMFB) circuit in order to maintain the balance. This paper presents improved characteristics of the CMFB circuit and designs the wide-bandwidth CMOS Op-amp. The unity gain bandwidth of this Op-amp is 50MHz with the load capacitor 2pF, and the value of phase margin is $85^{\circ}$.