• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.600-603
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• 2008

본 논문은 액정 표시 소자 (liquid crystal display, LCD)의 저소비 전력을 위한 새로운 메모리-인-픽셀 회로 설계를 제안한다. 각 픽셀 (화소)이 한 개의 메모리를 가지고 있기 때문에 이러한 회로는LCD동작을 위해 게이트와 소스 구동 회로의 동작 없이도 메모리에 저장된 데이터를 이용하여 8컬러를 표현할 수 있다. 즉 구동 회로의 동작 없이도 각 화소에 내장된 메모리를 이용하여 데이터를 표현할 수 있기 때문에 LCD패널의 소비전력을 줄일 수 있다. 각 메모리 회로는 각 화소에 내장된 수정된 S-R플립플롭(NAND형)으로 구성되어 있고, 플립플롭은 겹치지 않는 클럭 CLK_A와 CLK_B를 이용하여 교류 바이어스를 공급한다. NAND형은 인버터형 메모리에 비해 회로는 더 복잡하지만, 약 50%의 더 낮은 소비전력 특성을 가진다. $96{\times}128$의 해상도를 가진 LCD패널에 대해 인버터형 메모리가 0.037 mW의 소비전력을 보인 반면 제안된 메모리 회로는 단지 0.007mW의 우수한 소비전력을 보였다.

• 전자공학회논문지B
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• 제29B권1호
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• pp.67-75
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• 1992

A new method of driving the PDP(Plasma Display Panel) was proposed and its characteristics were investigated. Applying high frequency non-discharge pulses to an auxiliary anode resulted an increased region of stable operation, decreased delay time and increased light intensity. It is suggested that PDP with DPM (Double Pulse Memory) drive technique improves the delay time, luminance, region of stable operation and luminous efficacy compared to PDP with PPM(Planar Pulse Memory) drive technique developed by NHK Lab. in Japan.

• 한국초등과학교육학회지:초등과학교육
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• 제27권3호
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• pp.244-251
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• 2008

One of the problems with testing for the presence of $CO_2$ is that the results are not visible. In order to over-come this weak point, a new testing method was developed with BTB indicator equipment, that made the gas visible. After that, the experiment was performed and tested the effects of the new visible equipment. The visible equipment could be adapted to regular class use successfully. Also, it was effective in that it reduced waste of gas, minimized danger potential through use of $CO_2$ canisters and candle-sticks, and also increased knowledge about indicators. The new experimental method and equipment affected the students' interest. It is possible that the students' positive participation was due to their interest in the new apparatus and application of the visual senses. The new system was tested fer its effects on teaching content and helping to produce sustained memory of the content. There were no significant differences between the groups in terms of content learning on initial content memory. However, when students in both groups were tested 4 months later, the visual experiment group sustained memory performance, while the other group showed a significant decrease. Generally, boys score higher than girls in terms of interest and participation in experimental activities. In this case, however, there were no difference between groups. It may have been due to introduction of new equipment and different methods from the textbooks. So, this could increase participation in science using various experiments.

• 한국디자인학회:학술대회논문집
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• 한국디자인학회 2003년도 봄 학술발표대회논문집
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• pp.16-17
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• 2003

• 한국지능시스템학회논문지
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• 제15권5호
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• pp.632-638
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• 2005

This paper describes a new data-handing, based on a Spatial Human Interface as human indicator, to the Spatial-Knowledge-Tags (SKT) in the spatial memory the Spatial Human Interface (SHI) is a new system that enables us to facilitate human activity in a working environment. The SHI stores human activity data as knowledge and activity history of human into the Spatial Memory in a working environment as three-dimensional space where one acts, and loads them with the Spatial-Knowledge-Tags(SKT) by supporting the enhancement of human activity. To realize this, the purpose of SHI is to construct new relationship among human and distributed networks computers and sensors that is based on intuitive and simultaneous interactions. In this paper, the specified functions of SKT and the realization method of SKT are explained. The utility of SKT is demonstrated in designing a robot motion control.

• ETRI Journal
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• 제26권6호
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• pp.615-621
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• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• 제어로봇시스템학회논문지
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• 제10권2호
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.473-482
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• 2017

Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.

• 전기전자학회논문지
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• 제11권4호
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• pp.193-197
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• 2007

We use a saturation function with memory instead of a pure saturation function to generate a limit cycle in order to find one point information of a plant in the frequency domain. The saturation function with memory is useful in the presence of noise and/or a short duration of short duration of external disturbances. We analyze the error caused by the approximation that the saturation function with memory treated as a pure saturation function. We propose a new tuning formula for PID controller which can be applied a saturation function having memory with an arbitrary memory size. We show that the proposed method is more accurate than that of the approximation method via an example.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.