• Title/Summary/Keyword: new memory

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A New Flash Memory Package Structure with Intelligent Buffer System and Performance Evaluation (버퍼 시스템을 내장한 새로운 플래쉬 메모리 패키지 구조 및 성능 평가)

  • Lee Jung-Hoon;Kim Shin-Dug
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.2
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    • pp.75-84
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    • 2005
  • This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

Archival Memory on the Web: Web 2.0 Technologies for Collective Memory (웹에서의 기록과 기억: 집단 기억을 위한 웹 2.0 기술)

  • Sinn, Dong-Hee
    • Journal of the Korean BIBLIA Society for library and Information Science
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    • v.23 no.2
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    • pp.45-68
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    • 2012
  • Archives have directly and indirectly served for memory. What is collected in archives, how it is presented to users, and how users understand and use the documents affects how a given society remembers its past. Some archival scholars see that how users interpret documents from their perspectives and by social interests may play a central role in constructing social memory because memories are often triggered by individual and social concerns of the present time. Therefore, knowing what causes users to seek for a certain materials, how they use those materials and why can offer a clue to learn how archives serve for social memory. In the Web space, the interaction between users and archives/archival materials can be easily observed. Beyond making access simple for users and promoting archival documents using Web technology, archives can serve the broader purpose of memory by skillfully exploiting the characteristics of Web 2.0 and digital cultures in a way to observe how users engage in and contribute to archival contents available on the Web. This study examines the discourses on memory in the archival context, and in particular, how archives can serve as platforms for memory within the new environment of Web 2.0 technologies. It surveys discussions on memory in relation to archives, history, and evidence, focusing on the user and use context as it is represented in the archival literature. This paper discusses how that technology provides features that allow us to see collective memory being constructed in the archives, and presents examples of how the Web 2.0 technology can structure the way users share their memories in building a larger narrative around the archive.

Memory Reduction Method of DIT-based IFFT Bit-Reversal (DIT 기반 IFFT의 Bit-Reversal 메모리 감소 기법)

  • Kim, Jun-Ho;Piao, Zheyan;Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.5
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    • pp.66-73
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    • 2015
  • IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

A Page Placement Scheme of Smartphone Memory with Hybrid Memory (이기종 메모리로 구성된 스마트폰 메모리의 페이지 배치 기법)

  • Lee, Soyoon;Bahn, Hyokyung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.1
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    • pp.149-153
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    • 2020
  • This paper presents a new page placement policy for DRAM/NVRAM hybrid main memory in smartphones. Unlike previous studies on hybrid memory systems, this paper performs the placement of pages based on the offline analysis of memory access behaviors as smartphone's memory accesses are skewed to a certain address ranges, which is consistent regardless of smartphone applications, specially for write operations. Thus, we aim at reducing the write traffic to NVRAM by the offline analysis results. Experimental results show that the proposed policy reduces the write traffic to NVRAM by 61% on average without performance degradations.

A Mobile Flash File System - MJFFS (모바일 플래시 파일 시스템 - MJFFS)

  • 김영관;박현주
    • Journal of Information Technology Applications and Management
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    • v.11 no.2
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    • pp.29-43
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    • 2004
  • As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.

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A Flash Memory Swap System for Mobile Computers (모바일 컴퓨터를 위한 플래시 메모리 스왑 시스템)

  • Jeon, Seon-Su;Ryu, Yeon-Seung
    • Journal of Korea Multimedia Society
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    • v.13 no.9
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    • pp.1272-1284
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    • 2010
  • As the mobile computers are becoming powerful and are used like general-purpose computers, operating systems for mobile computers also require swap system functionality that utilizes main memory efficiently. Flash memory is widely used as storage device for mobile computers but current linux swap system does not consider flash memory. Swap system is tightly related with process execution since it stores the contents of process in execution. By taking advantage of this characteristics, in this paper, we study a new linux swap system called PASS(Process-Aware Swap System), which allocates the different flash memory blocks to each process. Trace-driven experimental results show that PASS outperforms existing linux swap system with existing garbage collection schemes in terms of garbage collection cost.

An Effective Parallel ALPG for High Speed Memory Testing Using Instruction Analyzer (명령어 분석기를 이용한 고속 메모리 테스트를 위한 병렬 ALPG)

  • Yoon, Hyun-Jun;Yang, Myung-Hoon;Kim, Yong-Joon;Park, Young-Kyu;Park, Jae-Seok;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.33-40
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    • 2008
  • As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.

Digital Libraries as Scocio-Technical Interaction Networks: American Memory Project as one example of it (사회기술상호작용망(STIN)으로서의 디지털 도서관: American Memory Project를 중심으로)

  • Joung, Kyoung-Hee
    • Journal of the Korean Society for information Management
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    • v.20 no.4 s.50
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    • pp.91-111
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    • 2003
  • This paper shows that digital libraries can be understood through STIN models which emphasize interactions among components in networks. The enrollment strategies in the American Memory make human and non-human factors interact. Specifically, this paper articulates that the relationships between users and collections, between users and staff, and between users and users are closely linked through the strategies . Observing the linkages among these components ,this paper found that the enrollment processes not only draw users to the American Memory, but also alter roles of components and creates new roles and players for them. The alterations of roles and the resulting changes of relationships among components mean that digital libraries lead to transform the grounding of knowledge works in a society.

A novel hardware design for SIFT generation with reduced memory requirement

  • Kim, Eung Sup;Lee, Hyuk-Jae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.2
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    • pp.157-169
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    • 2013
  • Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.