• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권3호
• /
• pp.356-363
• /
• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

• 세라미스트
• /
• 제21권2호
• /
• pp.4-18
• /
• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• 스마트미디어저널
• /
• 제11권2호
• /
• pp.77-83
• /
• 2022

뉴로모픽 아키텍처는 스파이킹 신경망(SNN, Spiking Neural Network) 모델을 사용하여, 추론 실험을 통해 스파이크 값이 많이 누적될수록 정확한 결과를 도출한다. 추론 결과가 특정 값으로 수렴할 경우, 추론 실험을 더 진행해도 결과의 변화가 작아 소비 전력이 더 커질 수 있다. 특히, 인공지능 기반 IoT 환경에서는 전력 낭비는 큰 문제가 될 수 있다. 따라서 본 논문에서는 뉴로모픽 아키텍처 환경에서 추론 이미지 노출 시간을 조절하여 추론 시간을 단축함으로써 인공지능 기반 IoT의 전력 낭비를 줄이는 기법을 제안한다. 제안한 기법은 추론 정확도의 변화를 반영하여 다음 추론 이미지 노출 시간을 계산한다. 또한, 추론 정확도의 변화량 반영비율을 계수 값으로 조절할 수 있으며, 다양한 계수 값의 비교 실험을 통해 최적의 계수 값을 찾는다. 제안한 기법은 목표 정확도에 해당하는 추론 이미지 노출 시간은 선형 기법보다 크지만 최종 추론 시간은 선형 기법보다 적다. 제안한 기법의 성능을 측정하고 평가한 결과, 제안한 기법을 적용한 추론 실험이 선형 기법을 적용한 추론 실험보다 최종 노출 시간을 약 90% 단축할 수 있음을 확인한다.

• 한국인터넷방송통신학회논문지
• /
• 제21권5호
• /
• pp.71-77
• /
• 2021

최근 이질적인 하드웨어 특성을 고려한 IoT 응용 지원 프레임워크의 효율적인 프로그램 개발이 요구되고 있다. 또한, 인간의 뇌를 모사하여 스스로 학습 및 자율적 컴퓨팅이 가능한 뉴로모픽 아키텍처의 발전으로 하드웨어 지원의 범위가 넓어지고 있다. 하지만 기존 대부분의 IoT 통합개발환경에서는 AI(Artificial Intelligence) 기능을 지원하거나 뉴로모픽 아키텍처와 같은 다양한 하드웨어와 결합된 서비스 지원이 어렵다. 본 논문에서는 2세대 인공 신경망 및 3세대 스파이킹 신경망 모델을 모두 지원하는 AI 컴포넌트 추상화 모델을 설계하고 제안 모델 기반의 자율형 IoT 통합개발환경을 구현하였다. IoT 개발자는 AI 및 스파이킹 신경망에 대한 지식이 없어도 제안 기법을 통해 자동으로 AI 컴포넌트를 생성할 수 있으며 런타임에 따라 코드 변환이 유연하여 개발 생산성이 높다. 제안 기법의 실험을 진행하여 가상 컴포넌트 계층으로 인한 변환 지연시간이 발생할 수 있으나 차이가 크지 않음을 확인하였다.

• 센서학회지
• /
• 제29권1호
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• 한국전기전자재료학회논문지
• /
• 제35권4호
• /
• pp.311-321
• /
• 2022

The report reviews recent research efforts in demonstrating a computing system whose operation principle mimics the dynamics of biological neurons. The temporal variation of the membrane potential of neurons is one of the key features that contribute to the information processing in the brain. We first summarize the neuron models that explain the experimentally observed change in the membrane potential. The function of ion channels is briefly introduced to understand such change from the molecular viewpoint. Dedicated circuits that can simulate the neuronal dynamics have been developed to reproduce the charging and discharging dynamics of neurons depending on the input ionic current from presynaptic neurons. Key elements include volatile memristors that can undergo volatile resistance switching depending on the voltage bias. This behavior called the threshold switching has been utilized to reproduce the spikes observed in the biological neurons. Various types of threshold switch have been applied in a different configuration in the hardware demonstration of neurons. Recent studies revealed that the memristor-based circuits could provide energy and space efficient options for the demonstration of neurons using the innate physical properties of materials compared to the options demonstrated with the conventional complementary metal-oxide-semiconductors (CMOS).

• 한국표면공학회지
• /
• 제53권6호
• /
• pp.330-342
• /
• 2020

Since the original report on ferroelectricity in Si-doped HfO2 in 2011, fluorite-structured ferroelectrics have attracted increasing interest due to their scalability, established deposition techniques including atomic layer deposition, and compatibility with the complementary-metal-oxide-semiconductor technology. Especially, the emerging fluorite-structured ferroelectrics are considered promising for the next-generation semiconductor devices such as storage class memories, memory-logic hybrid devices, and neuromorphic computing devices. For achieving the practical semiconductor devices, understanding polarization switching kinetics in fluorite-structured ferroelectrics is an urgent task. To understand the polarization switching kinetics and domain dynamics in this emerging ferroelectric materials, various classical models such as Kolmogorov-Avrami-Ishibashi model, nucleation limited switching model, inhomogeneous field mechanism model, and Du-Chen model have been applied to the fluorite-structured ferroelectrics. However, the polarization switching kinetics of fluorite-structured ferroelectrics are reported to be strongly affected by various nonideal factors such as nanoscale polymorphism, strong effect of defects such as oxygen vacancies and residual impurities, and polycrystallinity with a weak texture. Moreover, some important parameters for polarization switching kinetics and domain dynamics including activation field, domain wall velocity, and switching time distribution have been reported quantitatively different from conventional ferroelectrics such as perovskite-structured ferroelectrics. In this focused review, therefore, the polarization switching kinetics of fluorite-structured ferroelectrics are comprehensively reviewed based on the available literature.

• 전기전자학회논문지
• /
• 제28권2호
• /
• pp.234-238
• /
• 2024

본 논문은 낮은 구동 전류 특성과 3차원 적층 구조로 확장시킬 수 있는 장점을 가진 3차원 적층형 이중 팁 RRAM을 CNN 가속기 아키텍처에 접목하는 연구를 수행한 논문이다. 3차원 적층형 이중 팁을 적층 형태의 병렬연결로 시냅스 어레이에 사용하여 멀티-레벨을 구현하였다. 이를 Network-on-chip 형태의 가속기 내에 DAC, ADC, 버퍼 및 레지스터, shift & add 회로 등 다양한 하드웨어 블록들과 함께 구성하여 CNN 가속기에 대한 시뮬레이션을 수행하였다. 시냅스 가중치와 활성화 함수의 양자화는 16-bit으로 가정하였다. 해당 가속기 아키텍처를 위한 병렬 파이프라인을 통해 CNN 연산을 시뮬레이션한 결과, 연산효율은 약 370 GOPs/W를 달성하였으며, 양자화에 의한 정확도 열화는 3 % 이내가 되는 결과를 나타냈다.