• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.156-161
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• 2011

The present study introduces a novel wet etching technique for nanostructure fabrications which usually requires low surface roughness. Using the current method, acquired profiles were smooth even in the nanoscale, which cannot be easily achieved with conventional wet or dry etching methods. As one of the most popular single crystal silicon etchant, potassium hydroxide (KOH) solution was used as a base solvent and two additives, antimony trioxide (Sb2O3) and ethyl alcohol were employed in. Four experimental parameters, concentrations of KOH, Sb2O3, and ethyl alcohol and temperature were optimized at 60 wt.%, 0.003 wt.%, 10 v/v%, and $23^{\circ}C$, respectively. Effects of additives in KOH solution were investigated on the profiles in both (110) and (111) planes of single crystal silicon wafer. The preliminary results show that additives play a critical role to decrease etch rate significantly down to ~2 nm/min resulting in smooth side wall profiles on (111) plane and enhanced surface roughness.