• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.101-101
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• 2011

투명전도성산화물(transparent conducting oxides, TCOs) 박막으로써 널리 쓰이는 산화인듐주석(indium tin oxide, ITO)은 전기 전도성과 광 투과성이 우수하여 주로 유기발광다이오드(organic light-emitting diode, OLED)의 전극, 발광다이오드(light-emitting diode, LED)의 current spreading 층 및 태양전지(solar cell)의 윈도우층(window layer) 등의 광전자 소자로 응용되고 있으나, 고가의 indium 가격과 인체에 유해한 독성 등이 문제점으로 지적되고 있다. 따라서 indium의 함량을 저감한 새로운 조성의 TCO 또는 indium을 함유하지 않은 친환경적인 TCO 대체 재료 개발의 필요성이 증대되고 있다. 이러한 재료 중 하나인 AZO (Al-doped zinc oxide, $Al_2O_3$: 2 wt.%)는 3.82eV의 넓은 에너지 밴드갭을 가지며, 가시광선 및 근 적외선 파장 영역에 대하여 90% 이상의 높은 투과율을 나타낸다. 또한, 습식식각이 가능하며, 매우 풍부하여 원가가 매우 저렴하고, 독성이 없다. 본 연구에서는 박막 증착율이 높고, 제작과정의 조정이 용이한 RF magnetron 스퍼터를 이용하여 glass 기판 위에 AZO 박막을 성장하고, $N_2$ 분위기에서 다양한 온도 조건에서 열처리(rapid thermal annealing, RTA)하여 전기 및 광학적 특성에 대하여 비교 분석하였다. 또한, 이후에 기존의 성장방법과 달리 고가의 진공 장비를 사용하지 않고, 저온에서도 간단한 구조의 장비를 이용하여 균일한 나노구조를 성장시킬 수 있는 전기화학증착법(electrochemical deposition)으로 AZO 박막위에 ZnO 나노로드를 다양한 성장조건에 따라 성장시켜 광학적 특성을 비교 분석하였다.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.707-711
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• 2006

ZnO was doped up to 0.3 wt% for improving the electrical properties of lead-free $[Li_{0.04}(Na_{0.44}Ko_{0.52})-(Nb_{0.86}\;Ta_{0.10}\;Sb_{0.04})]O_3$ piezoelectric ceramics. The ceramics were fabricated with the conventional sintering processes. Crystal structure of the samples was tetragonal phase regardless of ZnO amount. However, the piezoelectric properties were varied with the ZnO amount. The electro-mechanical coupling factor $(k_p)$ was with the ZnO amount up to 0.2 wt% but decreased with the further addition. the maximum value of $k_p$ was 0.475. Density, piezoelectric charge constant and relative dielectric constant was also showed maximum value at 0.2 wt%. The maximum values are $4.75g/cm^3$, 275 pC/N, 1403, respectively. In contrast, the mechanical quality factor $(Q_m)$ was not varied with increasing the ZnO addition up to 0.2 wt% but rapidly increased at 0.3 wt%.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.800-806
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• 1997

The behavior of de levels in rapid thermal annealed Fe-doped semi-insulating InP(100) was studied by photoinduced current transient spectrocopy(PICTS). In bulk InP, T2(Ec-0.24 eV), T3(Ec-0.30 eV) and T5(Ec-0.62 eV) traps were observed. After annealing the T2 trap was annihilated at 20$0^{\circ}C$ and recreated at 35$0^{\circ}C$. T3 trap was not affected below 40$0^{\circ}C$. With increasing temperature the concentration of T5 trap reduced and it was annihilated at 30$0^{\circ}C$. However the T1(Ec-0.16 eV) and T4(Ec-0.42 eV) traps were began to appear at 40$0^{\circ}C$and these concentrations were increased with annealing temperature. The T1 and T4 traps seem to be related to the isolated phosphorus vacancy( $V_{p}$) and $V_{p}$-indium antisite( $V_{p}$- $P_{in}$ ) or $V_{p}$-indium interstitial( $V_{p}$-I $n_{I}$) respectiely.respectiely.

• Transactions on Electrical and Electronic Materials
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• v.6 no.3
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• pp.101-105
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• 2005

Electroluminescence(EL) and current-voltage(I-V) characteristics of hybrid EL devices containing Pr and Mn co-doped ZnS nanoparticles were investigated in this study. For the insertion of a hole transport layer of poly (N-vinyl carbazole)(PVK), the current level became lower due to the accumulation of electrons at the interface between PVK and nanoparticles. When both PVK and buffer layer $BaF_2$ were simultaneously introduced, the enhanced EL efficiency and improved I-V characteristics were obtained. This results from the additional increase of hole injection owing to the internal field induced by the significant accumulation of electrons at the interface. The presence of buffer layer $BaF_2$ together with PVK makes it possible the charge accumulation enough to induce the sufficient internal field for further hole injection.

• Journal of the Korean Ceramic Society
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• v.41 no.11
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• pp.826-833
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• 2004

In this study, photosensitivity dynamics in SiO$_2$ glass with the composition similar to that of silica Planar Lightwave Circuit (PLC) devices was investigated as a fundamental study prior to the device fabrication. Silica bulk glasses with similar composition to the core layer of PLC devices were prepared with variable composition of B$_2$O$_3$. The photosensitivity in boron and germanium co-doped SiO$_2$ glass yields refractive index change $\Delta$n as high as 10$\^$-3/. However such index modulation disappeared after annealing. From the result of annealing experiment and W absorption / Raman spectra, we conclude the compaction model is applicable to our glass system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.126-134
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• 1996

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.353-353
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• 2008

트랜지스터 속도는 현저하게 향상되어지는 반면에 RFICs(RF integrated circuits)는 대용량화, 고속화, 고집적화, 소형화, 고 효율화 온칩(on-chip) 수동소자의 부재에 의해 발전을 이루지 못하였다. 즉, 최근 전자기기의 집적화, 초소형화 됨에 따라 실장 밀도를 높이기 위해 부품의 소형화가 강하게 요구되는 동시에 Radio Frequency(RF)에서 이용가능한 수동소자인 capacitor를 개발하고자 본 논문에서는 손가락 모양(interdigital configuration)을 갖는 RF capacitor를 Ansoft사의 HFSS를 이용하여 이상적인 S-parameter, 정전용랑(capacitance), 손실계수(loss tangent)를 도출하고자 한다. 680um의 $Al_2O_3$ 기판에 BST doped MgO을 30um, Chromium과 gold를 각각 5um로 증착시켰다. 핑거 개수 (n, number), 핑거 길이(1, length), 핑거 간격(g, gap), 핑거 너비(w, width)를 변화 시켜가면서 이상적인 결과 값에 가까운 모양 (interdigital configuration)을 얻을 수 있었다. 핑거 수 3 개 일 때 입력 값에 대하여 손실 없는 출력 값(투과값)을 갖는 $S_{21}$이 1.5GHz에서 6dB이하로 떨어졌으며 핑거 간격이 줄고 핑거 너비가 커지고 핑거길이가 커질수록 높은 캐패시턴스 값을 갖는 것을 확인 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.7
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• pp.475-480
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• 2018

We investigated the tribological properties of amorphous carbon (a-C) films deposited with CrC interlayers of various thicknesses as the adhesive layer. A-C and CrC thin films were deposited using the unbalanced magnetron (UBM) sputtering method with graphite and chromium as the targets. CrC films as the interlayer were fabricated under a-C films, and various structural, surface, and tribological properties of a-C films deposited with various CrC interlayer thicknesses were investigated. With various CrC interlayer thicknesses under a-C films, the tribological properties of CrC/a-C films were improved; the increased film thickness exhibited a maximum high hardness of over 27.5 GPa, high elastic modulus of over 242 GPa, critical load of 31 N, residual stress of 1.85 GPa, and a smooth surface below 0.09 nm at the condition of 30-nm CrC thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.5
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• pp.411-416
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• 2006

A new reading technology for the ultra-high density data storage device utilizing AFM technology was proposed and its experimental results were discussed in this paper. For the experiments, an about $2{\mu}m$ thick conductive polymer layer was spin-coated on the heavily doped n-type Si wafer and an about $0.1{\mu}m$ thick PMMA layer was also been spin-coated on it. After then, the $5{\times}5$ memory way was fabricated by making indents on the surface of the wafer with the heated AFM tip, and the data reading was performed by scanning the surface with the tip biased at 10 V and the measuring the current flowing out at the end of the tip. The experimental results clearly showed that the new data reading technology worked superbly. The current measured was about 0.92 pA at the cell with the indent, and it was not only below 0.31 pA at the cell without the indent, but also at the cell where the indent was erased.