• Title/Summary/Keyword: multiple-valued logic systems

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A Study on Constructing the Multiple-Valued Logic Systems over Finite Fields using by the Decision Diagram (결정도(決定圖)에 기초(基礎)한 유한체상(有限體上)의 다치논리(多値論理)시스템구성(構成)에 관한 연구(硏究))

  • Park, Chun-Myoung
    • Journal of IKEEE
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    • v.3 no.2 s.5
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    • pp.295-304
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    • 1999
  • This paper presents a method of constructing the Multiple-Valued Logic Systems(MVLS) over Finite Fields(FF) using by Decision Diagram(DD) that is based on Graph Theory. The proposed method is as following. First, we derivate the Ordered Multiple-Valued Logic Decision Diagram(OMVLDD) based on the multiple-valued Shannon's expansion theorem and we execute function decomposition using by sub-graph. Next, we propose the variable selecting algorithm and simplification algorithm after apply the each isomorphism and reodering vertex. Also we propose MVLS design method.

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MVL-Automata for General Purpose Intelligent Model (범용 지능 모델을 위한 다치 오토마타)

  • 김두완;이경숙;최경옥;정환묵
    • Journal of the Korean Institute of Intelligent Systems
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    • v.11 no.4
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    • pp.311-314
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    • 2001
  • Recently, research on Intelligent Information Process has actively been under way JD various areas and gradually extended to be adaptive to uncertain and complex dynamic environments. This paper presents a Multiple Valued Logic Automata(MVL-Automata) Model, utilizing properties of difference in a Multiple Valued Logic function. That is, MVL-Automata is able to be autonomously adapted to dynamic changing since an input stling is mapped to the value of a Multiple Valued Logic function and the property of difference in a Multiple Valued Logic function is applied to state transition. Therefore, Multiple Valued Logic Automata can be widely applied to the modeling dynamically of changing environments.

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An Emotion Processing Model using Multiple Valued Logic Functions (다치 논리함수를 이용한 감성처리 모델)

  • Chung, Hwan-Mook
    • Journal of the Korean Institute of Intelligent Systems
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    • v.19 no.1
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    • pp.13-18
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    • 2009
  • Usually, human emotions are vague and change diversely on the basis of the stimulus from the outside. Plutchik classified the fundamental behavioral patterns into eight patterns, named each of them a genuine emotion, and furthermore suggested mixed emotions using a combination of genuine emotions. In this paper, we propose a method for processing Plutchik's emotion model using Multiple Valued Logic(MVL) Automata Model which utilizes the properties of difference in Multiple Valued Logic functions. This proposed emotion processing model can be widely applied to the analysis and processing of emotion data.

Image Recognition by Learning Multi-Valued Logic Neural Network

  • Kim, Doo-Ywan;Chung, Hwan-Mook
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.2 no.3
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    • pp.215-220
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    • 2002
  • This paper proposes a method to apply the Backpropagation(BP) algorithm of MVL(Multi-Valued Logic) Neural Network to pattern recognition. It extracts the property of an object density about an original pattern necessary for pattern processing and makes the property of the object density mapped to MVL. In addition, because it team the pattern by using multiple valued logic, it can reduce time f3r pattern and space fer memory to a minimum. There is, however, a demerit that existed MVL cannot adapt the change of circumstance. Through changing input into MVL function, not direct input of an existed Multiple pattern, and making it each variable loam by neural network after calculating each variable into liter function. Error has been reduced and convergence speed has become fast.

Pattern Recognition Using BP Learning Algorithm of Multiple Valued Logic Neural Network (다치 신경 망의 BP 학습 알고리즘을 이용한 패턴 인식)

  • 김두완;정환묵
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2002.12a
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    • pp.502-505
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    • 2002
  • 본 논문은 다치(MVL:Multiple Valued Logic) 신경망의 BP(Backpropagation) 학습 알고리즘을 이용하여 패턴 인식에 이용하는 방법을 제안한다. MVL 신경망을 이용하여 패턴 인식에 이용함으로서, 네트워크에 필요한 시간 및 기억 공간을 최소화할 수 있고 환경 변화에 적응할 수 있는 가능성을 제시하였다. MVL 신경망은 다치 논리 함수를 기반으로 신경망을 구성하였으며, 입력은 리터럴 함수로 변환시키고, 출력은 MIN과 MAX 연산을 사용하여 구하였고, 학습을 하기 위해 다치 논리식의 편 미분을 사용하였다.

A Multiple-Valued Fuzzy Approximate Analogical-Reasoning System

  • Turksen, I.B.;Guo, L.Z.;Smith, K.C.
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1993.06a
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    • pp.1274-1276
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    • 1993
  • We have designed a multiple-valued fuzzy Approximate Analogical-Reseaning system (AARS). The system uses a similarity measure of fuzzy sets and a threshold of similarity ST to determine whether a rule should be fired, with a Modification Function inferred from the Similarity Measure to deduce a consequent. Multiple-valued basic fuzzy blocks are used to construct the system. A description of the system is presented to illustrate the operation of the schema. The results of simulations show that the system can perform about 3.5 x 106 inferences per second. Finally, we compare the system with Yamakawa's chip which is based on the Compositional Rule of Inference (CRI) with Mamdani's implication.

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A Study on Constructing the Multiple-Valued Combinational Logic Systems by Decision Diagram (결정 다이아그램에 의한 다치조합논리시스템 구성에 관한 연구)

  • 김이한;김성대
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.6
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    • pp.868-875
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    • 1995
  • This paper presents a method of constructing the multiple-valued combinational logic systems(MVCLS) by decision diagram. The switching function truth table of MVCLS is transformed into canonical normal form of sum-of-products(SOP) with literals at first. Next, the canonical normal form of SOP is transfered into multiple-valued logic decision diagram(MVLDD). The selecting of variable ordering is very important in this stage. The MVLDDs are quite different from each other according to the variable ordering. Sometimes the inadequate variable ordering produces a very large size of MVLDD means the large size of circuit implementation. An algorithm for generating the proper variable ordering produce minimal MVLDD and an example shows the verity of the algorithm. The circuits are realized with T-gate acceording to the minimal MVLDD.

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Multiple-valued FFT processor design using current mode CMOS (전류 모드 CMOS를 이용한 다치 FFT 연산기 설계)

  • Song, Hong-Bok;Seo, Myung-Woong
    • Journal of the Korean Institute of Intelligent Systems
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    • v.12 no.2
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    • pp.135-143
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    • 2002
  • In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

A Study on the Construction of Multiple-Valued Logic Functions by Edge-Valued Decision Diagram (에지값 결정도(決定圖)에 의한 다치논리함수구성(多値論理函數構成)에 관한 연구(硏究))

  • Han, Sung-Il;Choi, Jai-Sock;Park, Chun-Myoung;Kim, Heung-Soo
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.111-119
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    • 1997
  • This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

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A study on the construction of multiple-valued logic functions and full-adders using by the edge-valued decision diagram (에지값 결정도에 의한 다치논리함수구성과 전가계기설계에 관한 연구)

  • 한성일;최재석;박춘명;김흥수
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.3
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    • pp.69-78
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    • 1998
  • This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently using in constructing the digital logic systems based on the graph theory. We discussed the function minimization method of the n-variables multiple-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm. We showed the EMVDD of Full Adder by module construction and verified the proposed algorithm by examples. The proposed method has the visible, schematical and regular properties.

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