• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of KIISE:Software and Applications
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• v.31 no.6
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• pp.808-816
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• 2004

This paper proposes the method of implementation of practical online face verification system based on multiple feature combination and a similarity space. The main issue in face verification is to deal with the variability in appearance. It seems difficult to solve this issue by using a single feature. Therefore, combination of mutually complementary features is necessary to cope with various changes in appearance. From this point of view, we describe the feature extraction approaches based on multiple principal component analysis and edge distribution. These features are projected on a new intra-person/extra-person similarity space that consists of several simple similarity measures, and are finally evaluated by a support vector machine. From the experiments on a realistic and large database, an equal error rate of 0.029 is achieved, which is a sufficiently practical level for many real- world applications.

• The Journal of the Acoustical Society of Korea
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• v.22 no.4E
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• pp.176-182
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• 2003

As the needs for wireless Internet service is increasing, the needs for secure m-commerce is also increasing. Conventional security techniques are reinforced by biometric security technique. This paper utilized the voice as biometric security techniques. We developed speaker verification system for m-commerce (mobile commerce) via wireless internet and wireless application protocol (WAP). We named this system the mVprotek. We implemented the system as client-server architecture. The clients are mobile phone simulator and personal digital assistant (PDA). The verification results are obtained by integrating the mVprotek system with SK Telecom's code dimension multiple access (CDMA) system. Utilizing f-ratio weighting and virtual cohort model normalization showed much better performance than conventional background model normalization technique.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.5
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• pp.84-89
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• 2007

This research was done on the basis of assumption that there is a relationship between welding parameters and geometry of the back-bead being a gap in arc welding. Multiple regression analysis was used as method for predicting the geometry of the back-bead. The analysis data and the verification data were used for the formation of multiple regression analysis. The method was used to perform the prediction of the back-bead.

• Journal of the Korean Society of Systems Engineering
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• v.19 no.1
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• pp.56-63
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• 2023

For the success of system development, it is necessary to systematically manage the requirements that are the basis of system development and its verification results. In order to follow the principles of SE(Systems Engineering)-based V&V(Verification&Validation) process, requirements can be managed by securing the requirements and their establishments, design compliances, and verification compliances according to the system development lifecycle. Especially, in a large-complex system research and development project, such as a space launch vehicle development project, many participants establish, verify, and validate numerous requirements together during the project. Therefore, logical and systematic requirements management, including guarantee of data integrity, change history, and traceability, is very important for multiple participants to utilize numerous requirements together without errors. This paper introduces the practical requirements and verification management for the requirements-based development process in the space launch vehicle development project.

• Journal of Distribution Science
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• v.14 no.3
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• pp.23-30
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• 2016

Purpose - This research focuses on the analysis of logistics barriers in Korea, China and Japan facing the barriers of overseas-expanded manufacturers with other countries. With the tree countries are emerging as the biggest trade partners in Northeast Asia, their logistics barriers are applied with similar verification methods of preceding researches such as Carter(1997). Research design, data and methodology - Collecting the statistics data from the three countries' overseas-expanded manufacturers, t-verification was performed in order to analyze average value and verify any significance. Additionally, multiple regression analysis was used to analyze any influence on the relationship in Korean logistics barrier and Chinese and Japanese expansion to Korean market. Results - Statistics suggested that three countries' logistics barriers are significantly differentiated by each verification categories, and Korean barrier negatively affected Chinese and Japanese manufacturers coming into Korean market. Conclusions - As a result of multiple regression analysis of the influencing relationship between Korea's logistics barrier and Chinese and Japanese companies coming into Korean market, all of the Korean barriers are affecting the companies as an obstructive factor, and it is proved to be statistically meaningful. Therefore, in order to reduce Chinese and Japanese companies' cost burden, it is necessary that not only reasonable charge system and taxation support but also comprehensive measure establishment reduce Korea's logistics barriers. However, since this research has a limitation in samples and shows a period of 5 years in the three nations' trade barriers, continuous and complementary researches are necessary in order to develop certain objectivity.

• Radiation Oncology Journal
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• v.8 no.1
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• pp.111-114
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• 1990

External stereotaxic irradiation of intracranial lesions has recently gained its interest in the fields of not only radiation oncolgy but also neurosurgery. Its main goal is to deliver large doses to a relatively small target volume. Authors present methods of the stereotaxic radiosurgical irradiation using 6 MV linear accelerator (Nelac-6) and isodose distribution by therapeutic computer (Therac 2000). We attempt to demonstrate the dose distribution on verification films.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2609-2612
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• 2003

This paper describes a 64 channel signal generator/analyzer module that is useful for verification and testing of digital circuits. It can perform logic analyzer function and signal generator function at the same time. The 64 Channel module is implemented with single FPGA chip for miniaturization, and an USB interface is used to increase portability of the module. Multiple modules can be used in parallel for the verification of large scale circuits. Moreover, since the module is implemented as a PC based system, one can configure convenient GUI(Graphic User Interface) environment.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.417-422
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• 1993

Robots working in the multiple robot system can perform the variety of tasks compared to the single robot system, while they are subject to the various tight constraints such as the precise coordination and the mutual collision avoidance during the task execution. In this paper, we provide an algorithm and graphical verification for collision avoidance between two robots working together. The algorithm calculates the minimum time delay for collision avoidance and the graphical verification is performed through the 3-D graphic simulator.