• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3986-3994
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• 2000

A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] $\bigodot$,$\square$ [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction($\bigodot$). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction($\bigodot$) could be generated nearly in the almost same condensed time as the input components are fel>ded in the dyadic pipeline unitlo) or the output components are drained out of the dyadic pipeline unit($\square$), so called a dedicated chained pipeline unit for only a inner product operation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.5
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• pp.956-967
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• 2010

Rapid growth of internet applications has increased the importance of intrusion detection system (IDS) performance. String matching is the most computation-consuming task in IDS. In this paper, a new algorithm for multiple string matching is proposed. This proposed algorithm is based on the canonical Aho-Corasick algorithm and it utilizes a bidirectional and parallel processing structure to accelerate the matching speed. The proposed string matching algorithm was implemented and patched into Snort for experimental evaluation. Comparing with the canonical Aho-Corasick algorithm, the proposed algorithm has gained much improvement on the matching speed, especially in detecting multiple keywords within a long input text string.

• The KIPS Transactions:PartB
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• v.12B no.4 s.100
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• pp.507-512
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• 2005

There is a limitation of using a small number of input buttons for writing Hangul words on hand-held devices. As a quick and convenient way of implementing Hangul vowels by small number of buttons, we propose a vowel input system in which vowels are fabricated from eight vowels. Our input system supports a fast input speed by making all the diphthong from one or two strokes. It also adopts a multiple input method for diphthong that users can make a diphthong in a user-friendly way of vowel writing formation or pronunciation similarity. Furthermore, we added an error correction functionality for the similar vowels that are caused by vowel harmony rules. When the proposed method is compared to the previous ones, our method outperformed in the input speed and error correction.

• Journal of Communications and Networks
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• v.10 no.2
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• pp.186-193
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• 2008

A two-hop multiple-input multiple-output (MIMO) relay network which comprises a multiple antenna source, an amplify-and-forward MIMO relay and many potential users are studied in this paper. Consider the achievable sum rate as the performance metric, a joint design method for the processing units of the BS and relay node is proposed. The optimal structures are given, which decompose the multiuser MIMO relay channel into several parallel single-input single-output relay channels. With these structures, the signal-to-noise ratio at the destination users is derived; and the power allocation is proved to be a convex problem. We also show that high sum rate can be achieved by pairing each link according to its magnitude. The sum rate of three broadcast strategies, time division multiple access (TDMA) to the strongest user, dirty paper coding (DPC), and beamforming (BF) are investigated. The sum rate bounds of these strategies and the sum capacity (achieved by DPC) gain over TDMA and BF are given. With these results, it can be easily obtained that how far away TDMA and BF are from being optimal in terms of the achievable sum rate.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• ETRI Journal
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• v.26 no.5
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• pp.375-383
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• 2004

This paper proposes a common interleaving method associated with independent channel-encoding among transmitter antenna branches in orthogonal frequency and code division multiplexing based on multiple-input multiple-output (MIMO) multiplexing to achieve an extremely high throughput such as 1 Gbps using a 100 MHz bandwidth. This paper also investigates the average packet error rate performance as a function of the average received signal energy per bit-to-background noise power spectrum density ratio $(E_b/N_0)$. We found that the loss in the required average received $E_b/N_0$ of the proposed method is only within approximately 0.3 dB in up to a 12-path Rayleigh fading channel, using 16QAM and Turbo coding with a coding rate of 5/6. We also clarify that even for a large fading correlation among antenna branches, 1 Gbps is still possible by increasing the transmission power. Therefore, the proposed method reduces the processing rate to 1/4 in the turbo decoder with only a slight loss in the required average received $E_b/N_0$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.6
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.2
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• pp.51-64
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• 2004

This paper proposes an algerian of generating a tuner-template from multiple fingerprint impressions using a data fusion technique for fingerprint enrollment. The super-template is considered as a single fingerprint template which contains most likely true minutiae based on multiple fingerprint images. The proposed algorithm creates the super template by utilizing a recursive Bayesian estimation method (RBEM), which assumes a sequential fingerprint input model and estimates the credibility of the minutiae in previous input templates froma current input template. Consequently. the RBEM assigns a higher credibility to commonly detectable minutiae from several input templates and a lower credibility to rarely found minutiae from other input templates. Likewise, the RBEM is able to estimate a credibility of the minutia type (ridge ending or bifurcation). Preliminary experiments demonstrate that, as the number of fingerfrint images increases, the performance of recognition can be improved while maintaining the processing time and the size of memory storage for tile super-template almost constant.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.735-742
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• 2010

In this paper, we propose adaptive algorithms for interference cancellation in RF repeaters with multiple transmit and receive antennas. When multiple antennas are used in a repeater, the imperfect isolation between transmit and receive antennas causes the feedback interference which is modeled as multi-input multi-output (MIMO) channel. To remove the feedback interference, we derive the least mean square (LMS) algorithm and the recursive least squares (RLS) algorithm for interference cancellation based on adaptive signal processing techniques. Through computer simulations for the proposed algorithms, we analyze the convergence characteristics and compare the steady-state performance for interference cancellation.