• Journal of Korean Society of Water and Wastewater
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• v.27 no.6
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• pp.711-721
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• 2013

Optimal operation of a combined sewer network with distributed storage facilities aims to use the whole retention capacity of all reservoirs efficiently before overflows take place somewhere in the considered network system. An efficient real-time network control (RTNC) strategy has been emerging as an attractive approach for reducing substantially the overflows from a sewer network compared to the conventional fixed or manually adjusted gate setting method, but the related concrete framework for RTC development has not been throughly introduced so far. The main goal of this study is to give a detailed description of the RTNC systems via reviewing several guidelines published abroad, and finally to suggest methods for the proper application of RTNC on distributed storage facilities. Especially, this study is focused on emphasizing the importance of hierarchical structure of RTNC system that consists of three control layers (management, global control and local control). Further, with regard to the global control layer which is responsible for the central overall network control, the wide-ranging details of two components (adaption and optimization layers) are also presented. This study can provide the valuable basis for the RTNC implementation in the particular sewer network with distributed multiple storage facilities.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.1-6
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• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.

• Journal of Power Electronics
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• v.15 no.1
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• pp.131-145
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• 2015

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

• Journal of Power Electronics
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• v.14 no.4
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• pp.733-741
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• 2014

The integration of photovoltaic (PV) energy sources into DC grid has gained considerable attention because of its enhanced conversion efficiency with reduced number of power conversion stages. During the integration process, a local control unit is normally included with every power conversion stage of the PV source to accomplish the process of maximum power point tracking. A centralized monitoring and supervisory control unit is required for monitoring, power management, and protection of the entire system. Therefore, we propose a field-programmable gate array (FPGA) based centralized control unit that integrates all local controllers with the centralized monitoring unit. The main focus of this study is on the process of integrating many local control units into a single central unit. In this paper, we present design and optimization procedures for the hardware implementation of FPGA architecture. Furthermore, we propose a transient analysis and control design methodology with consideration of the nonlinear characteristics of the PV source. Hardware experiment results verify the efficiency of the central control unit and controller design.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.151-159
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• 2022

In this paper, we implement a digital multi-beamformer using FPGA(Field Programmable Gate Array) which has advantages in parallel and real-time data processing. This is accomplished through the use of not only high-speed data communication but also multiple beam forming, which is currently required by MFR(Multi Function Radar). As a result, the beamformer can process 24 Gbps throughput in real-time and form 5 digital beams at the same time. It is also compared to the results of Matlab simulations. We demonstrate how an implemented beamformer can be used in an MFR system by using a digital array antenna.

• Journal of Genetic Medicine
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• v.19 no.1
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• pp.27-31
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• 2022

X-linked dominant hypophosphatemic rickets are the most common form of familial hypophosphatemic rickets resulting from hypophosphatemia caused by renal phosphate wasting, which in turn is a result of loss-of-function mutations in PHEX. Herein, we report a 39-year-old female with short stature and skeletal deformities and 12-month-old asymptomatic daughter. The female has a history of multiple surgical treatments because of lower limb deformities. Her biochemical findings revealed low serum phosphorus levels with elevated serum alkaline phosphatase activity and normal serum calcium levels, suggesting presence of hypophosphatemic rickets. To identify the molecular causes, we used a multigene testing panel and found a mutation, c.667dup (p.Asp223GlyfsTer15), in PHEX gene. To the best of our knowledge, this is a novel mutation. A heterozygous form of the same variant was detected in daughter, who showed no typical symptoms such as bow legs, frontal bossing, or waddling gate, but presented early signs of impaired mineralization in both X-ray and biochemical findings. The daughter was initiated onto early medical treatment with oral phosphate supplementation and an active vitamin D analog. Because the daughter was genetically diagnosed based on a family history before the onset of symptoms, appropriate medical management was possible from early infancy.

• ETRI Journal
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• v.46 no.2
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• pp.277-289
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• 2024

In this paper, we describe a neural network-based application that recommends multiple items using dialog context input and simultaneously outputs a response sentence. Further, we describe a multi-item recommendation by specifying it as a set of clothing recommendations. For this, a multimodal fusion approach that can process both cloth-related text and images is required. We also examine achieving the requirements of downstream models using a pretrained language model. Moreover, we propose a gate-based multimodal fusion and multiprompt learning based on a pretrained language model. Specifically, we propose an automatic evaluation technique to solve the one-to-many mapping problem of multi-item recommendations. A fashion-domain multimodal dataset based on Koreans is constructed and tested. Various experimental environment settings are verified using an automatic evaluation method. The results show that our proposed method can be used to obtain confidence scores for multi-item recommendation results, which is different from traditional accuracy evaluation.