• Journal of Korea Multimedia Society
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• v.18 no.2
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1446-1459
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• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.669-670
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• 2006

This paper describes the functions and design technology of the T-DMB (Terrestrial Digital Multimedia Broadcasting) receiver. T-DMB is a novel broadcasting media that can provide high-quality video and audio services. In this paper, we will describe the VLSI implementation of RF, Baseband and Multimedia Chip for T-DMB Receiver. The designed DMB SoC has low power consumption and has been implemented using a standard-cell library in 0.18um CMOS technology.

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.255-258
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• 2009

최근 EDA 툴의 기술적인 향상과 반도체 공정의 발달로 IC 설계자들은 RISC 프로세서, DSP 프로세서, 메모리 등 많은 IP가 하나로 집적되는 SoC구조가 가능해졌다. 하지만 기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가진다. 이러한 문제점은 SoC 내부의 IP들이 많을수록 SoC 플랫폼의 전체 성능이 저하되어, CPU 자체의 속도보다는 효율적인 통신에 의해 성능이 좌우된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 성능을 향상시키기 위하여 크로스바 스위치버스 구조를 제안한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스 구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상됨을 확인하였다.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.439-445
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• 2001

In this paper, we suggest a method for dynamic generation of SMIL documents by user profiles on the web. Generated multimedia documents are based on the SMIL (Synchronized Multimedia Integration Language) that are recommended by the W3C. The method generates automatically XSLT documents according to user profiles. SMIL documents are produced on real-time by integration of the XSLT documents and the XML documents that are made already. Most of conventional web-based documents are based on the HTML that is difficult to support reusability of documents are relation among multimedia abject. However, the suggested method is based on the XML, and so it supports reusability of documents and produces efficiently various SMIL-based multimedia documents. Application for the suggested method are as follows; Electronic commerce, tele-lecture, a web-based document editing, etc.

• Journal of Digital Convergence
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• v.10 no.1
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• pp.59-66
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• 2012

The Multimedia Contents, such like movies, internet and so on, are the most effective teaching means for generation c[content] learners who are accustomed to the multimedia environment. First, the multimedia contents become appropriate materials in that they help the learners understand the culture and lifestyle of its country through practical and vivid information. Second, they are useful leaning tools for the students who prefer visual media to improve interest and understanding. Third, as students have the time for developing their own contents based on given information, they understand the contents better and also have a indirect learning experience of culture. This means that the learning using multimedia contents has an influence on students' academic achievement. As a result, it is desirable for the application and development of multimedia contents to be suggested as an effective teaching method for foreign culture.

• Journal of Multimedia Information System
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• v.3 no.3
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• pp.85-90
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• 2016

We firstly tried to understand consumers' purchasing tendencies and mainly focused on designing a platform model that offers integrated support. C2B (Customer to Business) orders integrate with a consumption platform of a B2C (Business to Customer) model, and integrated support aims at design, supply, processing, and distribution of a fashion business. All the information such as orders, sales, production, supply, and settlement of accounts is synchronized under the C2B, B2C, and O2O (Online to Offline) environment so that accurate information can be shared in real time. Our platform automatically handles with a net income of a product designer, manufacturer, and shipping company once shipping is confirmed.