• Journal of Navigation and Port Research
• /
• v.29 no.10 s.106
• /
• pp.859-863
• /
• 2005

This paper describes the improvement of power control characteristics of ship's emergency lighting power supply(SELPS), by which electric power is controlled extensively, and power ON-OFF is controlled and system parameter monitored in remote distance by PC serial communication. Proposed system is composed of step-down converter(SDC), emergency power supply circuit(EPSC), half bridge(HB) inverter, fluorescent lamp(FL) starting circuit, microprocessor control and multi communication circuit. Experimental works confirm that relative system stops when over current is detected and speedy and stable emergency power is supplied when main power source cut-off, and controls input power up to 35[$\%$] by adjusting pulse frequency of the HB inverter, and ON-OFF control of multiple SELS, real time transmission and monitor of parameters as to voltage, current, and power values are performed appropriately by PC communication.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.24 no.1
• /
• pp.50-60
• /
• 2021

For conventional AESA radars, DC-DC power modules using 300 Vdc have low efficiency, high volume, heavy weight, and high price, which have problems in modularity with T/R module groups. In this paper, to improve these problems, we propose a distributed DC-DC power module with high-voltage 800 Vdc and high-efficiency Step-down Converter. In particular, power requirements for modern and future marine weapons systems and sensors are rapidly evolving into high-energy and high-voltage power systems. The power distribution of the next generation Navy AESA radar antenna is under development with 1000 Vdc. In this paper, the proposed highvoltage, high-efficiency DC-DC power modules increase space(size), weight, power and cooling(SWaP-C) margins, reduce integration costs/risk, and reduce maintenance costs. Reduced system weight and higher reliability are achieved in navy and ground AESA systems. In addition, the proposed architecture will be easier to scale with larger shipboard radars and applicable to other platforms.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.1
• /
• pp.53-60
• /
• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of IKEEE
• /
• v.2 no.2 s.3
• /
• pp.278-284
• /
• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.2
• /
• pp.124-133
• /
• 2009

There are many different ID representation forms depending on the media or applications. In case of RFID tag, ID representation form must be followed by the rule of ISO/IEC 15962. In this study, we developed the efficient ID conversion algorithm between ID representation form on RFID tag and Internet. The main idea is on the use of XML based ID profiles and three step logical IDs forms. The algorithm was tested by the typical three kinds of real IDs such as EPC, ISO/IEC 15459 KKR Code, and mCode which are the typical meta-IDs can be defined in ISO/IEC 18000-6C tag.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.25 no.1
• /
• pp.15-19
• /
• 2005

Conventional eddy current testing has been used for the detection of the defect-like fatigue crack in the conductive materials, such as aluminum, which uses a sinusoidal signal with very narrow frequency bandwidth, Whereas, the pulsed eddy current method uses a pulse signal with a broad bandwidth. This can allow multi-frequency eddy current testing, and the penetration depth is greater than that of the conventional eddy current testing. In this work, a pulsed eddy current instrument was developed for evaluating the metal loss. The developed instrument was composed of the pulse generator generating the maximum square pulse voltage of 40V, an amplifier controlled up to 52dB, an A/D converter of 16 bit and the sampling frequency of 20 MHz, and an industrial personal computer operated by the Windows program. A pulsed eddy current probe was designed as a pancake type in which the sensing roil was located inside the driving roil. The output signals of the sensing roil increased rapidly wich the step pulse driving voltage かn off, and the latter part of the sensing coil output voltage decreased exponentially with time. The decrement value of the output signals increased as the thickness of the aluminum test piece increased.