• Journal of Platform Technology
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• v.10 no.2
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• pp.3-9
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• 2022

In this paper, to maximize the performance of the scatter communication in multi-core and many-core processors, a technique that considers the communication situation of the processing node is applied to a multi-core processor composed of 32 processing nodes. Since the existing scatter algorithm cannot recognize the communication conditions of the processing nodes, communication is generally performed according to an initially set transmission order. In this case, scatter communication starts only after the communication currently being performed by all processing nodes inside the processor is finished. The scatter communication performance was improved by this technique, and it was confirmed that there was a performance improvement of up to 78.93% compared to the existing algorithm through BFM simulation.

• The Journal of the Acoustical Society of Korea
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• v.24 no.4
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• pp.186-193
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• 2005

The Terrestrial Digital Multimedia Broadcasting (T-DMB) system supplies high quality audio comparable with VCD in 7 inch display and high quality audio comparable CD at the mobile reception environment T-DMB will launch commercial service at the middle of 2005. However the bandwidth for audio data and the number of channels are restricted to 128 kbps and 2 respectively in the current T-DMB standard because of the limitation of available bandwidth for multimedia data. This Paper Proposes a novel media processor structure for providing multi-channel audio contents oyer T-DMB system allowing backward compatibility with the legacy T-DMB receiver. Furthermore. we also Propose an adaptive receiver structure to supply optimal audio contents on various speaker configuration in T-DMB receiver. To provide multi-channel audio contents allowing backward comaptilbity with the legacy T-DMB receiver, the additional data for multi-channel audio are defined as a dependent stream of main audio stream. The OD strucure for control an additional multi-channel audio elementary stream is proposed without changing the BIFS of the legacy T-DMB system.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.68-77
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• 2012

As the system development environment moves from single core to multi core-based platforms, it becomes more important to maintain compatibility between single core-based implementations and multi core-based implementations. Moreover, it is very important to support real-time on multi core platforms especially in cases of embedded software or test equipments which need real-time as well as correctness. Since Windows operating system dopes not support real-time in itself, it has been supporting real-time using expensive third-party solutions such as RTX or INtime. So as to reduce this kind of development expenses, in this paper, we propose RTiK-MP(Real-Time implant Kernel-Multi Processor) which supports real-time on Windows using the Local APIC of x86 architectures, and evaluate the performance of the proposed RTiK-MP after deploying it on portable missile test equipments.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.45-54
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• 1993

Monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with asymmetric system parameters and multi-symmetric links are respectively considered. Each links is to be an independent M /M/ 1/ 1/ type. Markov modeling technique is used to represent a model of monitoring processor with FCFS steering protocol. Performance measures considered are ratio of monitored jobs in each link, availability of minitoring processor and throughput of virtual processor in each link. The value of the performance meausres are compared with existing and simulation results.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.61-66
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• 1992

In this paper, a method for implementing software for the control system with dual structure in processor module is proposed and implemented to enhance its reliability. In this implementation the multi-tasking function which is provided by a real-time operating system is applied. The overall softwre is divided into five tasks and is performed in each of the dual processor module, independently. By this, the processor module with dual structure can achieve a control objective and fault diagnostics effectively. An experimental result shows that the backup processor module can be substituted for the primary processor module immediately when it happens to fail, because data relating the failure information are exchanged continuously done via shared memories.

• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.2 s.21
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• pp.30-37
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• 2005

In this paper, we propose how to design a fire control system main control board for individual combat weapons using a small and low power processor. To design an electric board of small weapon systems, Size and power consumption are very important factors. We solved the problem using selection of an adaptive processor, introduction of MicroChipPackaging method, and separate design of a main board Also we applied these methods to make the fire control system for small arms.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• The KIPS Transactions:PartC
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• v.16C no.4
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• pp.417-422
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• 2009

Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.