• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.553-555
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• 2004

SoC 분야에서 온 칩 버스는 전체 시스템의 성능을 결정하는 중요한 요소이다. 이에 따라 최근 ARM 사에서는 고성능 온 칩 버스 구조인 ML(Multi-Layer) AHB 버스를 제안하였다. ML AHB 버스는 저전력 임베디드 시스템에 적합한 버스 구조로써 현재 널리 사용되고 있다. 하지만, 고가이기 때문에 ADK(AMBA$^{TM}$ Design kit) 구매에 대한 부담이 적지 않다. 본 논문은 ML AHB의 버스 구조인 버스 매트릭스 구현 및 ADK에서 제공되지 않는 테스트 환경 즉, Protocol Checker 및 Performance Monitor Module 구현에 관한 것이다.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.61-66
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• 2016

This paper presents the implementation for a network structure of railway cars using a point to point communication. Most of network's representative specifications for a train are the FIP (Field Bus), MVB (Multifunction Vehicle Bus), CAN and WTB (Wire Train Bus) which is used by ALSOM, SIEMENS and BOMBADIER as major in this field. These networks in a physical layer use a multi-drop method, connected from $1^{st}$ car to $n^{th}$ car of a train through a cable without any extra services such as an electric part, amplifier. However waveforms which is passed through a long cable in the multi-drop are distorted by a capacitance or resistance of the cable or environments. Also since using a cable connected directly from $1^{st}$ car to $n^{th}$ car, if over two trains make double head, it isn't easy to distinguish ID for each railway cars. So by using the point to point network per each car, it is able to reduce a distortion. Also since reducing distortion, this communication speed can be been higher and transmit and receive any packets more stably. Using proposed token in a packet, this can make ID per each railway car automatically. Finally experimental results show the good performance and effectiveness of the proposed method.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

• Journal of Korean Society for Geospatial Information Science
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• v.24 no.1
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• pp.9-16
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• 2016

As the need of eco-friendly transportation systems for sustainable development increases, public transport accessibility has been considered as an important element of transportation system design. When analyzing the accessibility, shortest path algorithms can be utilized to reflect the actual movement and we can obtain high resolution accessibility for all other stations on the network with shortest distance and time. This study used the algorithm improved by reflecting the penalty of number of transfers and waiting time of overlapped routes to get the accessibility. KTX Seoul Station is a target place and this algorithm is applied to multi-layer subway bus network of Seoul to calculate the accessibility, therefore this study presented the accessibility of KTX Seoul station by stations.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1595-1607
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• 2018

In this paper, a hierarchical control strategy is introduced to control a new three-port multidirectional DC-DC converter for integrating an energy storage system (ESS) to a bipolar DC microgrid (BPDCMG). The proposed converter provides a voltage-balancing function for the BPDCMG and adjusts the states of charge (SoC) of the ESS. Previous studies tend to balance the voltage of the BPDCMG buses with active sources or by transferring power from one bus to another. Furthermore, the batteries available in BPDCMGs were charged equally by both buses. However, this power sharing method does not guarantee efficient operation of the whole system. In order to achieve a higher efficiency and lower energy losses, a triple-layer hierarchical control strategy, including a primary droop controller, a secondary voltage restoration controller and a tertiary optimization controller are proposed. Thanks to the multi-functional operation of the proposed converter, its conversion stages are reduced. Furthermore, the efficiency and weight of the system are both improved. Therefore, this converter has a significant capability to be used in portable BPDCMGs such as electric DC ships. The converter modes are analyzed and small-signal models of the converter are extracted. Comprehensive simulation studies are carried out and a BPDCMG laboratory setup is implemented in order to validate the effectiveness of the proposed converter and its hierarchical control strategy. Simulation and experimental results show that using the proposed converter mitigates voltage imbalances. As a result, the system efficiency is improved by using the hierarchical optimal power flow control.