• The Journal of the Acoustical Society of Korea
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• v.20 no.5
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• pp.35-47
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• 2001

This paper describes an efficient harmonic-CELP speech coder by taking advantages of harmonic and CELP coders into account. According to frame voicing decision, the proposed harmonic-CELP coder adopts the RP-VSELP coder as a fast CELP in case of an unvoiced frame, or an improved harmonic coder in case of a voiced frame. The proposed coder has main features as follows: simple pitch detection, fast harmonic estimation, variable dimension harmonic vector quantization, perceptual weighting reflecting frequency resolution, fast harmonic synthesis, naturalness control using band voicing, and multi-mode. These features make the proposed coder require very low complexity, compared with HVXC coder To demonstrate the performance of the proposed coder, a 2.4 kbps coder has been implemented and compared with reference coders. From results of informal listening tests, the proposed coder showed good quality while requiring low delay and complexity.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.