• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1024-1034
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• 1998

Most public cryptosystem widely used in communication network are based on the exponentiation-arithmetic. But, cryptosystem has to use bigger and bigger key parameter to attain an adequate level of security. This situation increases both computation and time delay. Montgomery, yang and Kawamura presented a method by using the pre-computation, intermediately computing and table look-up on modular reduction. Coster, Brickel and Lee persented also a method by using the pre-computation on exponentiation. This paper propose to reduce computation of exponentiation with spare prime. This method is to enhance computation efficiency in cryptosystem used discrete logarithms.

• Journal of the Korea Institute of Military Science and Technology
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• v.2 no.1
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• pp.159-169
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• 1999

Recently a firewall is being employed to protect hacking by controlling the traffics. The security services in the firewall include authentication, access control, confidentiality, integrity, and audit trail. A token is adapted for authentication to the firewall. A token has a small battery within which has restricted power capacity, This paper proposes a novel cost-effective firewall token for hacking protecting on transmission control protocol/internet protocol (TCP/IP) based network. This paper proposes a fast exponentiation method with a sparse prime that take a major operation for a public-key crypto-system and a major power consumption in the token. The proposed method uses much less amount of modular operations in exponentiation that is reduced of battery's capacity or CPU's price in the token.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.2
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• pp.79-84
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• 2012

Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• The KIPS Transactions:PartC
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• v.15C no.6
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• pp.507-512
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• 2008

At a recent, enterprises based on online-service are established because of rapid growth of information network. These enterprises collect personal information and do customer management. If customers use a paid service, company send billing information to customer and customer pay it. Such circulation and management of information is big issue but most companies don't care of information security. Actually, personal information that was managed by largest internal open-market was exposed. For safe customer information management, this paper proposes the method that decrease load of RSA cryptography algorithm that is commonly used for preventing from illegal attack or hacking. The method for decreasing load was designed by Binary NAF Method and it can operates modular Exponentiation rapidly. We implemented modular Exponentiation algorithm using existing Binary Method and Windows Method and compared and evaluated it.

• Review of KIISC
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• v.2 no.3
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• pp.89-101
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• 1992

본 논문에서는 암호알고리듬 실현을 위해 요구되는계산량에 가장 큰 영향을 미치는 모듈러 지수(modular exponentiation)에 관한 여러가지 연산알고리듬을 분석 및 제시하고 그 예를 보인다. 본 논문에서 소개되는 연산알고리듬은 $X^n$(mod p)를 계산하기 위한 대표적 방식인 이진방식(binary method), 그리고 고리(chain)를 이용하는 파워트리 방식(power tree method)및 가산고리방식(addition chain method)등을 포함한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1739-1747
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• 2004

In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n$^{2}$ clock cycles since two modular multiplications for M$_{i}$ and P$_{i}$ in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4. SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.135-146
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• 1999

Most public key cryptosystems are constructed based on a modular exponentiation, which is further decomposed into a series of modular multiplications. We design a new systolic array multiplier to speed up modular multiplication using Montgomery algorithm. This multiplier with simple circuit for each processing element will save about 14% logic gates of hardware and 20% execution time compared with previous one.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.1
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• pp.43-48
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• 2004

This paper presents new architectures based on the linear feedback shia resister architecture over GF(2m). First we design a modular multiplier and a modular squarer, then propose an architecture by combing the multiplier and the squarer. All architectures use an irreducible AOP (All One Polynomial) as a modulus, which has the properties of all coefficients with '1'. The proposed architectures have lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponentiation architecture, which is the con operation in public-key cryptosystems.