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Efficient Radix-4 Systolic VLSI Architecture for RSA Public-key Cryptosystem  

Park Tae geun (가톨릭대학교 정보통신전자공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.12C, 2004 , pp. 1739-1747 More about this Journal
Abstract
In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n$^{2}$ clock cycles since two modular multiplications for M$_{i}$ and P$_{i}$ in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4. SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.
Keywords
RSA; Cryptosystem; Modular multiplication; Systolic;
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