• Title/Summary/Keyword: modem

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Implementation of a Multi-Protocol Baseband Modem for RFID Reader (RFID Reader용 멀티 프로토콜 모뎀 설계)

  • Moon, Jeon-Il;Ki, Tae-Hun;Bae, Gyu-Sung;Kim, Jong-Bae
    • The Journal of Korea Robotics Society
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    • v.4 no.1
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    • pp.1-9
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    • 2009
  • Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

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Implementation of DS-SS Modem-based Communication System for Long Distance Wireless-Transmission (원거리 무선전송을 위한 DS-SS 모뎀 기반의 통신시스템 구현)

  • Ju, Won-Ki;Kim, Yoon-Ho;Lee, Joo-Shin
    • Journal of Advanced Navigation Technology
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    • v.15 no.6
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    • pp.1075-1081
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    • 2011
  • In this paper, we proposed the DS-SS modem-based communication system for long distance wireless-transmission. The module we designed in this approach contained both convolution encoder and gold-code generator, which aimed at error correcting, T-DES encryption algorithm and spread-spectrum as well. It embodied PC-based GUI program in order to control the such command signal as data transceiver. This program also used to control the specific FPGA/MCU which is able to verify and interface to the modem. We demonstrated the communication system to verify its proper operation by using GUI program and designed hardware. A set of experiments are conducted and as a result, proposed communication system is well operated as the design specification.

PERFORMING OF SOC DATS INTERFACE TEST WITH MODEM/BB

  • Park, Durk-Jong;Hyun, Dae-Hwan;Koo, In-Hoi;Ahn, Sang-Il;Kim, Eun-Kyou
    • Proceedings of the KSRS Conference
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    • v.1
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    • pp.64-66
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    • 2006
  • DATS will connect with IMPS and LHGS to perform the reception of sensor data and the transmission of user's meteorological data, LRIT and HRIT. MODEM/BB will perform the de-commutation of received sensor data as MI and GOCI raw data according to VCID before sending them to MI and GOCI IMPS, respectively. Especially, MODEM/BB in SOC needs to be connected to six clients that consist of the primary and backup IMPS of MSC, KOSC and SOC. On the other hand, LRIT and HRIT delivered from LHGS are encoded as VITERBI and modulated by MODEM/BB. Considering sensor data transmitted from COMS, the assumed format and size of CADU are described in this paper. Finally, results related to the status of received LRIT and HRIT by frame synchronizer in user station are also described.

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Performance of 2-Carrier DS system and its MODEM designed for Power Line Transmission (전력선 통신을 위한 2-반송파 DS방식의 특성과 MODEM의 구현)

  • 김인태;이무영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.3
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    • pp.582-590
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    • 1994
  • This paper introduce a highly verstile and simple data transmission system designed for commercial power distribution lines. The system operates on the DSSS principle but utilizes two independent carrier frequencies each represents polarity of DS MODEM outiputs. At the receiving terminal, outputs of two envelope detectors are directly applied to separate DS correlators before the two components are compared. The recovered signals which represents data and line noise are then compared at comparator. With the noise power greatly rudused at the correlator, the error rate of the data observed at comparator desplays great improvement comparing to the conventional FSK-DS system in which the detector output are compared before the correlator stage. Despite its simplest structure, the prototype MODEM transmitts 2400 bps with the error rate 10 , about 10dB improved compared to conventional FSK system.

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Design and Implementation of an Ultrasonic Communication Modem for Underwater Sensor Networks (수중 센서네트워크를 위한 초음파 통신 모뎀 설계 및 구현)

  • Byeon, Moo-Kwang;Park, Sung-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.6A
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    • pp.437-444
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    • 2009
  • Underwater sensor networks (USN) for ocean development and disaster prevention have been emerged as one of interesting research topics recently. Since a high-speed and inexpensive communication modem is a prerequisite for deployment of USN, we design and implement an underwater modem by utilizing general-purpose waterproof ultrasonic sensors in this paper. We also make experiments in indoor and outdoor environment with two modems facing each other to conduct a point-to-point communication. According to the experiments, we can achieve the data rates of 1.5 kbps in a water tank and 2 kbps in a pond. Also, the maximum communication distance between two modems is about 30 meters. Besides, we conduct a point-to-multipoint experiment imitating USN by deploying a gateway, a sink node and three sensor nodes in a water tank.

A Study on the Implementation of a 40kbps Narrowband Powerline Communication Modem Using the Chirp Technique (Chirp 방식을 이용한 40kbps급 협대역 전력선 통신 모뎀 구현에 관한 연구)

  • Park, Sung-Wook;Ohm, Woo-Yong
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.42 no.4
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    • pp.53-62
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    • 2005
  • In this paper, we implement a 40kbps narrowband powerline communication modem which is able to high transfer rate than conventional powerline communication technology by using the chirp technique that is one of the spread spectrum techniques. A modem that implement in this paper used the CEBus standard and a symbol that the linear variable frequency signal of 100$\sim$380kHz is kept for 25us. Experimental results, we verified the possibility that communication technology with the Chirp technique can make transfer rate more than 40kbps at narrowband communication.

A Study on the optical MODEM Development for high Speed Data Transmission (고속 데이터 전송을 위한 광모뎀 개발에 관한 연구)

  • 은재정;권원현;김석희;박한규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.6
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    • pp.612-620
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    • 1987
  • In this paper, the optical modem for data link realization is designed with the advantages of optical fiber, large bandwidth, high speed and long haul communication. Modem interface, CCITT V.24 and EIA RS-232C is adopted for the compatibility with existing systems, and biphase coding format is used for digital modulation. And also, modem has serveral loopback test facility in order to diagnose system itself. Optical transmitter and receiver are designed to have the receiving sensitivity of -30dBm at $10^-9$BER in the short wavelength region. Developed system is capable of transmitting data rate at 1200bps up to 57.6Kbps in sync., and at any bps within DC to 200Kbps in async transmission.

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Design of Chip Set for CDMA Mobile Station

  • Yeon, Kwang-Il;Yoo, Ha-Young;Kim, Kyung-Soo
    • ETRI Journal
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    • v.19 no.3
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    • pp.228-241
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    • 1997
  • In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

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The Unified UE Baseband Modem Hardware Platform Architecture for 3GPP Specifications

  • Kwon, Hyun-Il;Kim, Kyung-Ho;Lee, Chung-Yong
    • Journal of Communications and Networks
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    • v.13 no.1
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    • pp.70-76
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    • 2011
  • This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

On the Design of Demodulator and Equalizer of 9600 BPS Modem (9600 BPS Modem의 복조기와 Equalizer에 관한 연구)

  • 장춘서;은종관
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.4
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    • pp.10-15
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    • 1983
  • In this paper effective methods of demodulation and equalization in a 9600 bps modem have been studied. To reduce the number of multiplications required per symbol in demodula-tion, the method of using a decimation filter is presented. In the equalizer the optimum step size and the steady state mean-squared error (MSE) are obtained from computer simulation results. The performance of the first-order carrier phase tracking loop is compared with that of the second-order loop when carrier frequency offset exists. In addition, the finite word length effects in the equalizer are studied.

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