• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.745-750
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• 2007

In this paper, we propose a new gate modification method using the input vector maximizes the number of gates in WLS within the optimum range of the minimum leakage power. We prove that MLV is not always the optimal solution, and that the leakage power and area can decrease when modifying the gates using the input vector for which the number of gates in WLS is maximized within the optimum range of the minimum leakage power for the circuits applying the IVC technique and gate modification method. Using the proposed method, the gate-level description circuit can be converted to the modified circuit which reduces the leakage power by chip designer, and the modified circuit can be applied without any modification in design flow.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.53-60
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• 2009

Due to increased integration density and reduced threshold voltages, leakage current reduction becomes important in the semiconductor IC design for low power consumption. In a combinational logic circuit, the leakage current in the standby state depends on the values of the input. In this research, we developed a new input vector control method to minimize the leakage power. A new efficient algorithm is developed to find the minimal leakage vector. It can reduce the leakage current by 15.7% from the average leakage current and by 6.7% from the results of simulated evolution method during standby or idle states for a set of benchmark circuits. The minimal leakage input vector, with idle input signal, can also reduce the leakage current by 6.8% from the average leakage current and by 3.2% from the results of simulated evolution method for sequential circuits.