• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.95-101
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• 2017

A simple and practical voltage balance method for a solid-state transformer (SST) is proposed to reduce the voltage difference of cascaded H-bridge converters. The tolerance device components in SST cause the imbalance problem of DC-link voltage in the H-bridge converter. The Max/Min algorithms of voltage balance controller are merged in the controller of an AC/DC rectifier to reduce the voltage difference. The DC-link voltage through each H-bridge converter can be balanced with the proposed control methods. The design and performance of the proposed SST are verified by experimental results using a 30 kW prototype.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.11
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• pp.1424-1428
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• 1999

This paper presents a mathematical decomposition coordination method to implementing the distributed optimal power flow (OPF), wherein a regional decomposition technique is adopted to parallelize the OPT. The proposed approach is based on the Alternating Direction Method (ADM), a variant of the conventional Augmented Lagrangian approach, and makes it possible the independent regional AC-OPF for each control area while the global optimum for the entire system is assured. This paper is an extension of our previous work based on the auxiliary problem principle (APP). The proposed approach in this paper is a completely new one, however, in that ADM is based on the Proximal Point Algorithm which has long been recognized as one of the attractive methods for convex programming and min-max-convex-concave programming. The proposed method was demonstrated with IEEE 50-Bus system.

• Journal of Power Electronics
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• v.15 no.3
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• pp.660-669
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• 2015

This paper presents a control scheme with a focus on the combination of phase disposition pulse width modulation (PDPWM) and DC capacitor voltage control for a chopper-cell based modular multilevel converter (MMC) for the purpose of eliminating the time-consuming voltage sorting algorithm and complex voltage balancing regulators. In this paper, the convergence of the DC capacitor voltages within one arm is realized by charging the minimum voltage module and discharging the maximum voltage module during each switching cycle with the assistances of MAX/MIN capacitor voltage detection and PDPWM signals exchanging. The process of voltage balancing control introduces no extra switching commutation, which is helpful in reducing power loss and improving system efficiency. Additionally, the proposed control scheme also possess the merit of a simple executing procedure in application. Simulation and experimental results indicates that the MMC circuit together with the proposed method functions very well in balancing the DC capacitor voltage and improving system efficiency even under transient states.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.738-749
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• 2011

In this paper, we study QoS(Quality of Service) control protocols and the effect using MAC/PHY parameters of client device in mobile network. We proposes the way of controling the bit-rate by estimating the channel condition of the client with measured MAC/PHY parameters which is sent from the client. With the proposed method, more accurate available bit-rate can be estimated compared to conventional protocol, RTCP(Real-time Transport Control Protocol). The accurate bit-rate estimation can decrease wasted bit-rate and transport delay. In the result of the advantages, the transported video quality can be enhanced. In this paper, we show the effects of enhancement using client's the field data measured in WiMAX.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9B
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• pp.563-568
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• 2007

This paper proposes a routing establishment method for improving path stability in mobile ad-hoc networks. In mobile ad-hoc networks, the network topology is highly dynamic due to the node mobility unlike wired networks. Since the existing methods are based on the shortest path algorithm with the minimum hop count regardless of the path stability, it could lead to packet loss and path disconnection in mobile ad-hoc networks. In particular, if control packets and critical data are transmitted on the unstable path, it causes serious problems. Therefore, this paper proposes one approach in order to minimize packet loss and path disconnection by considering the node mobility. After the destination node receives multiple RREQ messages, it selects the stable path through the proposed MinMax algorithm according to the node speed.

• Journal of Pharmaceutical Investigation
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• v.39 no.1
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• pp.65-71
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• 2009

The aim of the present study was to evaluate the bioequivalence of two domperidone maleate tablets, Motilium-$M^{(R)}$ Tablet (Janssen Korea Ltd., reference product) and $Toriem^{(R)}$ Tablet (Daewon Pharm. Co., Ltd., test product). Domperidone was extracted by liquid-liquid extraction using tert-butyl methyl ether and separated in less than 3 min on $C_{18}$ reverse-phase column using an isocratic elution. A tandem mass spectrometer, as detector, was used for quantitative analysis in positive mode by a multiple reaction monitoring mode to monitor the m/z $426.1{\rightarrow}119.1$ and the m/z $837.4{\rightarrow}158.2$ transitions for domperidone and the internal standard (roxithromycin), respectively. Calibration curves, from $0.05{\sim}50$ ng/mL of domperidone, showed correlation coefficients (r) higher than 0.9941. Intra day and inter day precision (C.V. %) for quality control were ranged from 10.04 to 16.09% and from 10.87 to 18.69%, respectively. The lower limit of quantification (LLOQ) of domperidone was 0.05 ng/mL. The method described is precise and sensitive and has been successfully applied to the study of bioequivalence of domperidone in 24 healthy Korean volunteers. Twenty-four healthy male Korean volunteers received a single dose of each medicine ($2{\times}12.72\;mg$ domperidone maleate) in a $2{\times}2$ crossover study. There was a one-week washout period between the doses. Plasma concentrations of domperidone were monitored for over a period of 24 hr after the administration. $AUC_{0-t}$ (the area under the plasma concentration-time curve) was calculated by the linear trapezoidal rule. $C_{max}$ (maximum plasma drug concentration) and $T_{max}$ (time to reach $C_{max}$) were compiled from the plasma concentration-time data. The 90% confidence intervals for the log transformed data were within acceptable range of log 0.8 to log 1.25 (e.g., $log\;0.92{\sim}log\;1.05$ for $AUC_{0-t}$, $log\;0.81{\sim}log\;1.05$ for $C_{max}$). The major parameters, $AUC_{0-t}$ and $C_{max}$ met the criteria of KFDA for bioequivalence indicating that $Toriem^{(R)}$ tablet is bioequivalent to Motilium-$M^{(R)}$ tablet.

• Journal of Power Electronics
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• v.10 no.5
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• pp.468-476
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• 2010

This paper proposes and develops a new direct voltage control (DVC) approach. This method is designed to be applied in various applications for AC drives fed with a three-phase voltage source inverter (VSI) working with a constant switching time interval as in the standard direct torque control (DTC) scheme. Based on a very strong min(max) criterion dedicated to selecting the inverter voltage vector, the developed DVC scheme allows the generation of accurate voltage forms of waves. The DVC algorithm is implemented on a dSPACE DS1104 controller board and then compared with the space vector pulse width modulation technique (SVPWM) in an open loop AC drive circuit. To demonstrate the efficiency of the developed algorithm in real time and in closed loop AC drive applications, a scalar control scheme for induction motors is successfully implemented and experimentally studied. Practical results prove the excellent performance of the proposed control approach.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.724-730
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• 1993

Most of clustering methods usually employ the center of a cluster to assign the input data into a cluster. When the shape of a cluster could not be easily represented by the center of cluster, however, it is difficult to assign input data into a proper cluster using previous methods. In this paper, to overcome such a difficulty, a cluster is to be represented as a collection of several subclusters. And membership functions are used to represent how much input data belong to subclusters. Then the position of each subcluster is adoptively corrected by use of a competitive learning neural network. To show the validity of the proposed method, a numerical example is illustrated, where FMMC(Fuzzy Min-Max Clustering) algorithm is compared with the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.3
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• pp.122-128
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• 2004

This paper presents a control approach for designing a fuzzy-PI controller for a synchronous generator excitation and SVC system. A combination of thyristor-controlled reactors and fixed capacitors(TCR-FC) type SVC is recognized as having the most flexible control and high speed response, which has been widely utilized in power systems, is considered and designed to improve the response of a synchronous generator, as well as controlling the system voltage. A Fuzzy-PI controller for SVC system was proposed in this paper. The PI gain parameters of the proposed Fuzzy-PI controller which is a special type of PI ones are self-tuned by fuzzy inference technique. It is natural that the fuzzy inference technique should be based on humans intuitions and empirical knowledge. Nonetheless, the conventional ones were not so. Therefore, In this paper, the fuzzy inference technique of PI gains using MMGM(Min Max Gravity Method) which is very similar to humans inference procedures, was presented and applied to the SVC system. The system dynamic responses are examined after applying all small disturbance condition.