• KIPS Transactions on Computer and Communication Systems
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• v.8 no.10
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• pp.245-250
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• 2019

The use of NAND flash memory has increased rapidly due to the development of mobile fields. However, NAND flash memory has a limited lifespan, so studies are underway to predict its lifespan. Workload is one of the factors that significantly affect the life of NAND flash memory, and workload analysis studies in mobile environments are insufficient. In this paper, we analyze the distribution of workload in the mobile environment by collecting traces generated by using Android-based smartphones. The collected traces can be divided into three groups of hotness. Also they are distributed in the form of heavy tails. We fit this to the Pareto, Lognormal, and Weibull distributions, and Traces are closest to the Pareto distribution.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.836-840
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• 2009

Many researchers have studied flash memory in order to replace hard disk storages. Many FTL algorithms have been proposed to overcome physical constraints of flash memory such as erase-before-write, wear leveling, and poor write performance. Therefore, these constraints should be considered for testing FTL algorithms and the performance evaluation of flash memory. As doing the experiments, we suffer from several problems with costs and settings in experimental configuration. When we, for example, replay the traces of Oracle to evaluate the I/O performance with flash memory, it is hard to extract exact traces of I/O operations in Oracle. Since there are only write operations in the log, it is impossible to gather read operations. In MySQL and SQLite, we can gather the read operations by changing I/O functions in the source codes. But it is not easy to search for the exact points about I/O and even if we can find out the points, we might get wrong results depending on how we modify source codes to get I/O traces. The FlaSim proposed in this paper removes the difficulties when we evaluate the performance of FTL algorithms and flash memory. Our Linux drivers emulate the flash memory as a hard disk. And we can easily obtain the usage statistics of flash memory such as the number of write, read, and erase operations. The FlaSim can be gracefully extended to support the additional modules implemented by novel algorithms and ideas. In this paper, we describe the structure of FTL emulator, development tools and operating methods. We expect this emulator to be helpful for many experiments and research with flash memory.

• The Journal of Art Theory & Practice
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• no.14
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• pp.217-245
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• 2012

The aim of this paper is to show how the paradigm of disaster resilience may help reorienting urban planning policies in order to mitigate various types of risks, thanks to carefully thought action on heritage and conservation practices. Resilience is defined as the "capacity of a social system to proactively adapt to and recover from disturbances that are perceived within the system to fall outside the range of normal and expected disturbances." It relies greatly on risk perception and the memory of catastrophes. States, regions, municipalities, have been giving territorial materiality to collective memory for centuries, but this trend has considerably increased in the second half of the 20th century. This is particularly true regarding the memory of disasters: for example, important traces of catastrophes such as urban ruins have been preserved, because they were supposed to maintain some awareness and hence foster urban resilience - Berlin's Gedachtniskirche is a well-known example of this policy. Yet, in spite of preserved traces of catastrophes and various warnings and heritage policies, there are countless examples of risk mismanagement and urban tragedies. Using resilience as a guiding concept might change the results of these failed risk mitigation policies and irrelevant disaster memory processes. Indeed, the concept of resilience deals with the complexity of temporal and spatial scales, and with partly emotional and qualitative processes, so that this approach fits the issues of urban memory management. Resilience might help underlining the complexity and the subtlety of remembrance messages, and lead to alternative paths better adapted to the diversity of risks, places and actors. However, when it is given territorial materiality, memory is almost always symbolically and politically framed and interpreted; Vale and Campanella had already outlined this political aspect of remembrance and resilience as a discourse. Resilience and the territorialization of memory are not ideologically neutral, but urban risk mitigation may come at that price.

• International journal of advanced smart convergence
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• v.12 no.1
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• pp.70-75
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• 2023

With the recent proliferation of memory-intensive workloads such as deep learning, analyzing memory access characteristics for efficient memory management is becoming increasingly important. Since read and write operations in memory access have different characteristics, an efficient memory management policy should take into accountthe characteristics of thesetwo operationsseparately. Although some previous studies have considered the different characteristics of reads and writes, they require a modified hardware architecture supporting read bits and write bits. Unlike previous approaches, we propose a software-based management policy under the existing memory architecture for considering read/write characteristics. The proposed policy logically partitions memory space into the read/write area and the write area by making use of reference bits and dirty bits provided in modern paging systems. Simulation experiments with memory access traces show that our approach performs better than the CLOCK algorithm by 23% on average, and the effect is similar to the previous policy with hardware support.

• Korean Architects
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• s.606
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• pp.114-117
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• 2019

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.431-438
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• 2019

Fileless malware uses memory injection attacks to hide traces of payloads to perform malicious works. During the memory injection attack, an attack named "process hollowing" is a method of creating paused benign process like system processes. And then injecting a malicious payload into the benign process allows malicious behavior by pretending to be a normal process. In this paper, we propose a method to detect the memory injection regardless of whether or not the malicious action is actually performed when a process hollowing attack occurs. The replication process having same execution condition as the process of suspending the memory injection is executed, the data set belonging to each process virtual memory area is compared using the fuzzy hash, and the similarity is calculated.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.6-10
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• 2023

High-potential data can be predicted and stored in the cache to prevent cache misses, thus reducing the processor's request and wait times. As a result, the processor can work non-stop, hiding memory latency. By utilizing the temporal/spatial locality of memory access, the prefetcher introduced to improve the performance of these computers predicts the following memory address will be accessed. We propose a prefetcher that applies the GRU model, which is advantageous for handling time series data. Display the currently accessed address in binary and use it as training data to train the Gated Recurrent Unit model based on the difference (delta) between consecutive memory accesses. Finally, using a GRU model with learned memory access patterns, the proposed data prefetcher predicts the memory address to be accessed next. We have compared the model with the multi-layer perceptron, but our prefetcher showed better results than the Multi-Layer Perceptron.