• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.281-285
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• 2011

One of the key issues in implementing RFID systems is to design anti-collision protocols for identifying all the tags in the interrogation zone of a RFID reader with the minimum identification delay. In this paper, Furthermore, in designing such protocols, the limited resources in tags and readers in terms of memory and computing capability should be fully taken into consideration. we first investigate two typical RFID anti-collision algorithms, namely RFID Gen2 Q algorithm (accepted as the worldwide standard in industrial domain) and FAFQ algorithm including their drawbacks and propose a new RFID anti-collision algorithm, which can improve the performance of RFID systems in terms of tag identification time considerably. Further, we compared performance of the proposed algorithm with Q algorithm and FAFQ algorithm through computer simulation.

• Journal of Korean Society for Geospatial Information Science
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• v.17 no.4
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• pp.61-66
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• 2009

This Paper describes a new program called DEM Generator need to process DEM from LiDAR data or digital map data. It is difficult to generate raster DEM from LiDAR mass point data sets and digital maps too large to fit into memory. The DEM Generator was designed to process DEM and shaded relief image of GeoTiff format in order of streaming meshes; I/O minimize tag, delaunay triangle, natural neighborhood or TIN, temporary files and grid. It is expected that we can be improved the precision of DEM and solved the time consuming problem of DEM generating of a wider area.

• ETRI Journal
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• v.33 no.3
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• pp.382-392
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• 2011

This paper proposes the streaming radio frequency identification (RFID) protocol to support robust data streaming in a passive communication, which is extended from the ISO18000-6 Type C RFID standard. By observing and modeling the unique bit error behavior through detailed analysis in this paper, we found that performance is significantly limited by inaccurate and unstable link frequencies as well as low SNR which are inevitable for passive devices. Based on the analysis, we propose a simple and efficient protocol to adaptively insert extra error control sequences in a packet for tolerating tough link condition while maximizing the throughput and preserving the minimal implementation cost. To evaluate effectiveness of our proposal in real-time streaming applications, we experimented on real-time H.264 video streaming and prototyped the system on FPGA. To our best knowledge, our paper is the first work to take analytical approach for maximizing the throughput and demonstrate the possibility of the realtime multimedia streaming transmission in the passive RFID system.

• ETRI Journal
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• v.35 no.4
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• pp.610-616
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• 2013

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 ${\mu}W$ at $V_{DD}=6$ V. It employs 222 transistors and occupies a chip area of 5.85 $mm^2$.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.189-198
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• 2015

Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

• Journal of KIISE
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• v.44 no.3
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• pp.306-313
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• 2017

Named entity recognition (NER) seeks to locate and classify named entities in text into pre-defined categories such as names of persons, organizations, locations, expressions of times, etc. Recently, many state-of-the-art NER systems have been implemented with bidirectional LSTM CRFs. Deep learning models based on long short-term memory (LSTM) generally depend on word representations as input. In this paper, we propose an approach to expand word representation by using pre-trained word embedding, part of speech (POS) tag embedding, syllable embedding and named entity dictionary feature vectors. Our experiments show that the proposed approach creates useful word representations as an input of bidirectional LSTM CRFs. Our final presentation shows its efficacy to be 8.05%p higher than baseline NERs with only the pre-trained word embedding vector.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.113-122
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• 2008

In RFID system, Middleware collects and filters streaming data gathered continuously from readers to process applications requests. The enormous amount of data makes middleware in highly overloaded. Hence, we propose reader level filtering in order to reduce overall middleware load. In this paper, we consider reader filtering capability and define query plan to minimize number of queries for processing into middleware and reader level. We design and implement middleware system based on proposed query plan. We perform several experiments on implemented system. Our experiments show that the proposed query plan considerably improves the performance of middleware by diminishing processing time and network traffic between reader and middleware.

• Korean Journal of Cognitive Science
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• v.19 no.1
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• pp.57-74
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• 2008

This study aimed to investigate the preferential brain activations involed in the set size during random number generation (RNG). The BNG condition gave more increased activations in the anterior cingulate cortex (ACC), inferior frontal gyrus (IFG), inferior parietal lobule (IPL), and superior temporal gyrus (STG) than the simple counting condition, which was a control rendition. When the activations were compared by the small set size condition versus the large set size condition, broad areas covering tempore-occipital network, ACC, and postcentral gyrus were more highly activated in the small set size condition than in the large set size condition, while responses of areas including medial frontal gyrus, superior parietal lobule, and lingual gyrus were more increased in the large set size condition than in the small set size condition. The capacity hypothesis of working memory fails to explain the results. On the contrary, strategy selection hypothesis seems to explain the current observations properly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.47-58
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• 1999

As the performance of processors improves, cache memories are used to overcome the difference of speed between processors and main memories. Generally cache memories are embedded and small sizes, fault coverage is a more important factor than test time in testing point of view. A new test algorithm and a new BIST architecture are developed to detect various fault models with a relatively small overhead. The new concurrent BIST architecture uses the comparator of cache management blocks as response analyzers for tag memories. A modified scan-chain is used for pre-testing of comparators which can reduce test clock cycles. In addition several boundary scan instructions are provided to control the internal test circuitries. The results show that the new algorithm can detect SAFs, AFs, TFs linked with CFs, CFins, CFids, SCFs, CFdyns and DRFs models with O(12N), where N is the memory size and the new BIST architecture has lower overhead than traditional architecture by about 11%.

• Journal of KIISE:Software and Applications
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• v.27 no.7
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• pp.759-768
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• 2000

The ZG-machine is a space-efficient G-machine, which exploits a simple encoding method, called tag-forwarding, to compress the heap structure of graphs. Experiments on the ZG-machine without garbage collection shows that the ZG-machine saves 30% of heap space and the run-time overhead is no more than 6% than the G-machine. This paper presents the results of further experiments on the ZG-machine with the garbage collector. As a result, the heap-residency of the ZG-machine decreases by 34% on average although the run-time increases by 34% compared to the G-machine. The high rate of the run-time overhead of the ZG-machine is incurred by the garbage collector. However, when the heap size is 7 times the heap-residency, the run-time overhead of the ZG-machine is no more than 12% compared to the G-machine. With the aspect of reduced heap-residency, the ZG-machine may be useful in memory-restricted environments such as embedded systems. Also, with the development of a more efficient garbage collector, the run-time is expected to decrease significantly.