• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.41-49
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• 2008

This paper presents a design of the control block of a passive UHF RFID tag IC according to EPCglobal Class-1 Generation-2 UHF RFID 1.1.0 Protocol. The control block includes a PIE block, CRC5/CRC16, a Slot Counter, a Random Number Generator, a Main Control Block, a Encoder and a Memory Interface. The control block has been designed using the Verilog HDL and has been simulated. Functional simulation results for the overall control block operation show that 11 instructions with 7 states are operated correctly. Also, the control block has been implemented with 36,230 gates by Synopsys Design Compiler and Apollo using Magnachip 0.25$\mu$m technology.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.545-554
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• 2006

RFID could be applied in the various fields such as distribution beside, circulation, traffic and environment on information communication outside. So this can speak as point of ubiquitous computing's next generation technology. However, it is discussed problem of RFID security recently, so we must prepare thoroughly about RFID security for secure information. In this paper, we proposed a method which could protect private information and ensure RFID's identification effectively storing face feature information on RFID tag. Our method which is improved linear discriminant analysis has reduced dimension of feature information which has large size of data. Therefore, we can sore face feature information in small memory field of RFID tag. Our propose d algorithm has shown 92% recognition rate in experimental results and can be applied to entrance control management system, digital identification card and others.

• 한국정보컨버전스학회:학술대회논문집
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• 2008.06a
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• pp.47-52
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• 2008

A radio-frequency identification(RFID) tag is a small, inexpensive microchip that emits an identifier in response to a query from a nearby reader. The price of these tags promises to drop to the range of $0.05 per unit in the next several years, offering a viable and powerful replacement for barcodes. The challenge in providing security for low-cost RFID tags is that they are computationally weak devices, unable to perform even basic symmetric-key cryptographic operations. Security researchers often therefore assume that good privacy protection in RFID tags is unattainable. In this paper, we explore a notion of minimalist cryptography suitable for RFID tags. We consider the type of security obtainable in RFID devices with a small amount of rewritable memory, but very limited computing capability. Our aim is to show that standard cryptography is not necessary as a starting point for improving security of very weak RFID devices. Our contribution is threefold: 1. We propose a new formal security model for authentication and privacy in RFID tags. This model takes into account the natural computational limitations and the likely attack scenarios for RFID tags in real-world settings. It represents a useful divergence from standard cryptographic security modeling, and thus a new view of practical formalization of minimal security requirements for low-cost RFID-tag security. 2. We describe protocol that provably achieves the properties of authentication and privacy in RFID tags in our proposed model, and in a good practical sense. Our proposed protocol involves no computationally intensive cryptographic operations, and relatively little storage. 3. Of particular practical interest, we describe some reduced-functionality variants of our protocol. We show, for instance, how static pseudonyms may considerably enhance security against eavesdropping in low-cost RFID tags. Our most basic static-pseudonym proposals require virtually no increase in existing RFID tag resources.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.130-136
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• 2008

This paper describes a low-power high-performance analog front-end block for $UHF(860{\sim}960MHz)$ band RFID tag chips. It satisfies ISO/IEC 18000-6 type C(EPCgolbal class1. generation2.) and includes a memory block for test. For reducing power consumption, it operates with a internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator has an error rate as low as 0.014%. It is designed using a 0.18um CMOS technology. The simulation results show that the designed circuit can operate properly with an input as low as $0.2V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.59-64
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• 2002

In the RFID system using ISM-band, The tag mounted at the object has used the DC power by rectifying the RF signals of the small antenna for operating the micro-controller and memory. The performance of the tag would be reduced because of the second harmonics generated by the nonlinearity of the semiconductor and the spurious signal excited the high order mode of the antenna. This paper has realized the novel type low-pass filter with "the Stub-I type DGS slot structure" to improve the efficiency of the tag by suppressing the harmonics. The optimized frequency character at the pass-band/stop-band has obtained by tuning the stub width and slit width of I type slot. The measured result of the LPF has the cutoff frequency 3.25 GHz, the insertion loss about -0.29~-0.3 dB at pass-band 2.4 GHz~2.5 GHz, the return loss about -27.688~-33.665 dB at pass-band with a good performance, and the suppression character is about -19.367 dB at second harmonics frequency 4.9 GHz. This DGS LPF may be applied the various application as the RFID, WLAN to improve the efficiency of the system by suppressing the harmonics and spurious signals. 

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.46-54
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• 2006

Recently, the important of a personal identification is increasing according to expansion using each on-line commercial transaction and personal ID-card. Although a personal ID-card embedded RFID(Radio Frequency Identification) tag is gradually increased, the way for a person's identification is deficiency. So we need automatic methods. Because RFID tag is vary small storage capacity of memory, it needs effective feature extraction method to store personal biometrics information. We need new recognition method to compare each feature. In this paper, we studied the face verification system using Hippocampal neuron modeling algorithm which can remodel the hippocampal neuron as a principle of a man's brain in engineering, then it can learn the feature vector of the face images very fast. and construct the optimized feature each image. The system is composed of two parts mainly. One is feature extraction using NMF(Non-negative Matrix Factorization) and LDA(Linear Discriminants Analysis) mixture algorithm and the other is hippocampal neuron modeling and recognition simulation experiments confirm the each recognition rate, that are face changes, pose changes and low-level quality image. The results of experiments, we can compare a feature extraction and learning method proposed in this paper of any other methods, and we can confirm that the proposed method is superior to the existing method.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.151-154
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• 2007

This paper describes the project for constructing a traceability system for producing using RFID antenna in 900MHz frequency band and the consideration. In this project we reviewed analysis of properties classified by production process and RFID system through each frequency band, and designed a single unit RFID reader including antenna. The developed antenna is optimized to a field condition and this paper will show the test results. Also, we designed a single unit RFID reader by adding a reader to a designed antenna and explained the rule of tag memory allocation. Lastly, after running the system we could calculate visible and invisible effects of operation results and check up a wide possibility of application for RFID.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.972-982
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• 1988

In multiprocessor systems, there are Omega network and M network among various MIN's which interconnect the processor and memory modules. Both one-path Omega network and two-path M network are composed of Log2N stages. In this paper, Augmented M network (AMN) with 2**k+1 paths and Augmented Omega network (AON) with 2**k paths are proposed. The proposed networks can be acomplished by adding K stage(s) to M network and Omega network. Using destination tag, routing algorithm for AMN and AON becomes simple and multiple faults are tolerant. By evaluating RST(request service time) performance of AMN and AON with (Log2N)+K stages, we demonstrated the fact that MMIN (AMN) with 2**k+1 paths performs better than MMIN(AON) with 2**k+1. paths.

• Journal of information and communication convergence engineering
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• v.5 no.4
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• pp.311-315
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• 2007

This paper proposes a revised query tree algorithm in RFID systems. The proposed QT_ecfi algorithm revises the QT algorithm, which has a memory-less property. In the QT_ecfi algorithm, the tag will send the remaining bits of their identification codes when the query string matches the first bits of their identification codes. When the reader receives all the responses of the tags, it knows which bit is collided. If the collision occurs in the last bit, the reader can identify two tags simultaneously without further query. While the tags are sending their identification codes, if the reader detects a collision bit, it will send a signal to the tags to stop sending. According to the simulation results, the QT_ecfi algorithm outperforms the QT algorithm in terms of the number of queries and the number of response bits.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.