• 전기전자학회논문지
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• 제24권4호
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• pp.1172-1175
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• 2020

차량에 사용되는 ECU에는 CPU 코어, 차량통신 콘트롤러, 메모리 인터페이스, 센서 인터페이스, I/O 인터페이스 등이 집적되어 있다. 현재 사용되는 차량용 ECU는 대부분 자사만의 독점적 프로세서 아키텍쳐로 개발하였으나, 최근 자율주행자동차 및 커넥티드카에서 소프트웨어 범용성을 위해 ARM, RISC-V와 같은 표준 프로세서를 기반으로 한 차량용 ECU의 수요가 급증하고 있다. 본 논문에서는 명령어 집합이 무료로 공개된 RISC-V를 기반으로 하여 주차 보조 시스템에 사용하기 위한 차량용 ECU를 설계하였다. 개발된 ECU는 32b RISC-V CPU 코어, CAN, LIN 등의 IVN 콘트롤러, ROM, SRAM 등의 메모리 인터페이스, SPI, UART, I2C 등의 I/O 인터페이스를 내장하였다. 65nm CMOS 공정에서 구현한 결과는 동작 주파수 50MHz, 면적 0.37㎟, 게이트 수 55,310개였다.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 1996년도 추계연구발표회 논문개요집
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• pp.28-29
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• 1996

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 동계학술연구발표회 및 스핀트로닉스와 나노물리에관한 국제심포지움
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• pp.250-251
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• 2007

• 대기
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• 제22권1호
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• pp.109-115
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• 2012

We parallelized the CFD_NIMR model, which is a numerical meteorological model, for best performance on both of distributed and shared memory parallel computers. This hybrid parallelization uses MPI (Message Passing Interface) to apply horizontal 2-dimensional sub-domain out of the 3-dimensional computing domain for distributed memory system, as well as uses OpenMP (Open Multi-Processing) to apply vertical 1-dimensional sub-domain for utilizing advantage of shared memory structure. We validated the parallel model with the original sequential model, and the parallel CFD_NIMR model shows efficient speedup on the distributed and shared memory system.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.865-870
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• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• 전기학회논문지
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• 제68권2호
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• Journal of Information Technology Applications and Management
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• 제29권5호
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• pp.27-37
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• 2022

This study intends to link agricultural machine history data with related organizations or collect them through IoT sensors, receive input from agricultural machine users and managers, and analyze them through AI algorithms. Through this, the goal is to track and manage the history data throughout all stages of production, purchase, operation, and disposal of agricultural machinery. First, LSTM (Long Short-Term Memory) is used to estimate oil consumption and recommend maintenance from historical data of agricultural machines such as tractors and combines, and C-LSTM (Convolution Long Short-Term Memory) is used to diagnose and determine failures. Memory) to build a deep learning algorithm. Second, in order to collect historical data of agricultural machinery, IoT sensors including GPS module, gyro sensor, acceleration sensor, and temperature and humidity sensor are attached to agricultural machinery to automatically collect data. Third, event-type data such as agricultural machine production, purchase, and disposal are automatically collected from related organizations to design an interface that can integrate the entire life cycle history data and collect data through this.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.59-64
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• 1994

The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.