• Journal of Internet Computing and Services
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• v.7 no.6
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• pp.105-112
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• 2006

This paper be composed to file system by making a new i_node structure which can decrease Write frequency because this's can improved the file system efficiency if reduced Write operation frequency of flash memory in respect of file system, i-node is designed to realize Cleaning policy of data in order to perform Write operation. This paper suggest Cleaning Algorithm for Write operation through a new i_node structure. In addition, this paper have mode the oldest data cleaned and the most recent data maintained longest as a result of experiment that the recent applied program and data tend to be implemented again through the concept of regional and time space which appears automatically when applied program is implemented. Through experiment and realization of the Flash file system, this paper proved the efficiency of NAND-type flash file system which is required in on Embedded system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.11
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• pp.7541-7548
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• 2015

Wireless Sensor Networks is the technology which is used in explore role for military purposes, as well as various fields such as industrial equipment management, process management, and leverage available technologies by distributing node into various areas. but there are some limitations about energy, processing power, and memory storage capacity in wireless sensor networks environment, because of tiny hardware, so various routing protocols are proposed to overcome it. however existing routing protocols are very vulnerable in the intercommunication, because they focus on energy efficiency, and they can't use existing encryption for it, Because of sensor's limitations such like processing power and memory. Therefore, this paper propose mutual authentication scheme that prevent various security threats by using mutual authentication techniques and, Key generation and updating system as taking into account energy efficiency.

• Journal of the Korea Society of Computer and Information
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• v.28 no.5
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• pp.155-161
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• 2023

97.5% of our country's exports and 87.2% of imports are transported by sea, making ports an important component of the Korean economy. To efficiently operate these ports, it is necessary to improve the short-term prediction of port water volume through scientific research methods. Previous research has mainly focused on long-term prediction for large-scale infrastructure investment and has largely concentrated on container port water volume. In this study, short-term predictions for petroleum and liquefied gas cargo water volume were performed for Ulsan Port, one of the representative petroleum ports in Korea, and the prediction performance was confirmed using the deep learning model LSTM (Long Short Term Memory). The results of this study are expected to provide evidence for improving the efficiency of port operations by increasing the accuracy of demand predictions for petroleum and liquefied gas cargo water volume. Additionally, the possibility of using LSTM for predicting not only container port water volume but also petroleum and liquefied gas cargo water volume was confirmed, and it is expected to be applicable to future generalized studies through further research.

• Journal of Mechanical Science and Technology
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• v.20 no.1
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• pp.110-124
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• 2006

The multi scale wavelet-Galerkin method implemented in an adaptive manner has an advantage of obtaining accurate solutions with a substantially reduced number of interpolation points. The method is becoming popular, but its numerical efficiency still needs improvement. The objectives of this investigation are to present a new numerical scheme to improve the performance of the multi scale adaptive wavelet-Galerkin method and to give detailed implementation procedure. Specifically, the subdomain technique suitable for multiscale methods is developed and implemented. When the standard wavelet-Galerkin method is implemented without domain subdivision, the interaction between very long scale wavelets and very short scale wavelets leads to a poorly-sparse system matrix, which considerably worsens numerical efficiency for large-sized problems. The performance of the developed strategy is checked in terms of numerical costs such as the CPU time and memory size. Since the detailed implementation procedure including preprocessing and stiffness matrix construction is given, researchers having experiences in standard finite element implementation may be able to extend the multi scale method further or utilize some features of the multiscale method in their own applications.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.35-42
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• 2003

We have studied DC energy conversion of RF card by wireless communication. In order to attain an objective, it used the system which is a Rectenna. The main purpose of energy conversion system is the operation of the circuits at RF-ID system. The proposed RF-ID system is a lot classified with the reader and tag. Reader is a kind of the base station role supporting RF energy. And priority tag convert RF energy from the reader it was delivered with a wireless to DC energy. The energy which is converted like Tag. It transmits to the reader characteristic ID of each card. The tag is mainly divided into rectifier, power module, memory and controller. The FRAM maintains the data like a ROM in no-power situation. And the advantage is a low power element compared with other EEPROM. There are two considerations, when RF energy is converted into DC source by wireless. One is energy amount supported from the reader, the other is high power efficiency. This paper presents a study of simulation and experiments on the RF-DC conversion circuit in tag by the power efficiency concentrated.

• Structural Engineering and Mechanics
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• v.38 no.4
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• pp.429-441
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• 2011

In large-scale problem, a huge size of computational resources is needed for a reliable solution which represents the detailed description of dynamic behavior. Recently, eigenvalue reduction schemes have been considered as important technique to resolve computational resource problems. In addition, the efforts to advance an efficiency of reduction scheme leads to the development of the multi-level system condensation (MLSC) which is initially based on the two-level condensation scheme (TLCS). This scheme was proposed for approximating the lower eigenmodes which represent the global behavior of the structures through the element-level energy estimation. The MLSC combines the multi-level sub-structuring scheme with the previous TLCS for enhancement of efficiency which is related to computer memory and computing time. The present study focuses on the implementation of the MLSC on the direct time response analysis and the frequency response analysis of structural dynamic problems. For the transient time response analysis, the MLSC is combined with the Newmark's time integration scheme. Numerical examples demonstrate the efficiency of the proposed method.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.115-116
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• 2000

Influence of sustain pulse-width on electro-luminous efficiency is experimentally investigated for surface discharge of AC-PDP. It is found that the firing voltage is decreased as the pulse-width is increased from $2\;{\mu}s$ to $8\;{\mu}s$ with sweeping frequency range of 10 kHz to 50 kHz. It has been found that the optimal sustain pulse-width is in the range of $3{\sim}4\;{\mu}s$ under driving frequency range of 30 kHz and 50 kHz, based on observations of memory coefficient, wall charge, and wall voltage as well as luminous efficiency.

• Journal of the Korean Data and Information Science Society
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• v.10 no.2
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• pp.473-483
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• 1999

We introduce a way to construct a supercomputing capable system with some networked PCs, running the Linux operating system and computing power comparable with expensive commercial workstations, and with the Parallel Virtual Machine (PVM) software which enables one to control the total CPUs and memories of the networked PCs. By benchmarking the system using a PVM parallel program, we find that the system's parallel efficiency is close to 90 %.

• Journal of the Korea Society of Computer and Information
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• v.23 no.10
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• pp.1-9
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• 2018

Modern graphics processing units (GPUs) have become one of the most attractive platforms in exploiting high thread level parallelism with the support of new programming tools such as CUDA and OpenCL. Recent GPUs has applied cache hierarchy to support irregular memory access patterns; however, L1 data cache (L1D) exhibits poor efficiency in the GPU. This paper shows that the L1D does not always positively affect the applications in terms of performance and energy efficiency for the GPU. The performance of the GPU is even harmed by using the L1D for lots of applications. Our proposed technique exploits the characteristics of the currently-executed applications to predict the performance impact of the L1D on the GPU and then decides whether to continuously use the cache for the application or not. Our experimental results show that the proposed technique improves the GPU performance by 9.4% and saves up to 52.1% of the power consumption in the L1D.

• Journal of Information Processing Systems
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• v.17 no.1
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• pp.51-62
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• 2021

On-chip caches of graphics processing units (GPUs) have contributed to improved GPU performance by reducing long memory access latency. However, cache efficiency remains low despite the facts that recent GPUs have considerably mitigated the bottleneck problem of L1 data cache. Although the cache miss rate is a reasonable metric for cache efficiency, it is not necessarily proportional to GPU performance. In this study, we introduce a second key determinant to overcome the problem of predicting the performance gains from L1 data cache based on the assumption that miss rate only is not accurate. The proposed technique estimates the benefits of the cache by measuring the balance between cache efficiency and throughput. The throughput of the cache is predicted based on the warp occupancy information in the warp pool. Then, the warp occupancy is used for a second bypass phase when workloads show an ambiguous miss rate. In our proposed architecture, the L1 data cache is turned off for a long period when the warp occupancy is not high. Our two-level bypassing technique can be applied to recent GPU models and improves the performance by 6% on average compared to the architecture without bypassing. Moreover, it outperforms the conventional bottleneck-based bypassing techniques.