• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04a
• /
• pp.155-158
• /
• 2000

Influence of sustain pulse-width on electro-luminous efficiency is experimentally investigated for surface discharge of AC-PDP. A square pulse with variable duty ratio and rising time of 300 ns has been used in the experiment. It is found that the firing voltage is decreased as the pulse-width is increased from 2 ${\mu}s$ to 8 ${\mu}s$ with sweeping frequency range of 10 kHz to 50 kHz. It has been found that the optimal sustain pulse-width is in the range of $3{\sim}4{\mu}s$ under driving frequency range of 30 kHz and 50 kHz, based on observation of memory coefficient, wall charge, and wall voltage as well as luminous efficiency.

• Journal of KIISE:Computing Practices and Letters
• /
• v.14 no.2
• /
• pp.241-245
• /
• 2008

Non-volatile RAM (NVRAM) has both characteristics of nonvolatility and byte addressability. In order to efficiently exploit this NVRAM in the file system layer, we proposed the MiNV (Metadata in NVram) file system in our previous research. MiNV file system maintains all the metadata in NVRAM while storing file data in NAND Flash memory. In this paper, we experimentally analyze the efficiency for the execution of garbage collection in the MiNV file system. Also, we quantify the file system performance gains obtained from efficient garbage collection. Experimental results show that garbage collection on the MiNV file system executes more efficiently that on YAFFS even though these file systems adopt exactly the same garbage collection policy. Specifically, the MiNV file system invokes the aggressive garbage collection mechanism less frequently than YAFFS. Additionally, the MiNV file system postpones the first execution of the aggressive garbage collection mechanism in our experiments. From the experiments, we verify that the efficiency of garbage collection leads to performance improvements of the MiNV file system.

• Journal of the Optical Society of Korea
• /
• v.10 no.1
• /
• pp.1-10
• /
• 2006

Optical transparency and high diffraction efficiency are two essential factors for high performance of the photopolymer. Optical transparency mainly depends on the miscibility between polymer binder and photopolymerized polymer, while diffraction efficiency depends on the refractive index modulation between polymer binder and photopolymerized polymer. For most of organic materials, the large refractive index difference between two polymers accompanies large structural difference that leads to the poor miscibility and thus poor optical quality via light scattering. Therefore, it is difficult to design a high-performance photopolymer satisfying both requirements. In this work, first, we prepared a new phase-stable photopolymer (PMMA) with large refractive index modulation and investigated the optical properties. Our photopolymer is based on modified poly (methyl methacrylate) as a polymer binder, acryl amide as a photopolymerizable monomer, triethanolamine as initiator, and yellow eosin as a photosensitizer at 532 nm. Diffraction efficiency over 85% and optical transmittance over 90% were obtained for the photopolymer. Second, Organic-inorganic nanocomposite films were prepared by dispersing an aromatic methacrylic monomer and a photo- initiator in organic-inorganic hybrid sol-gel matrices. The film properties could be controlled by optimizing the content of an organically modified silica precursor (TSPEG) in the sol-gel matrices. The photopolymer film modified with the organic chain (TSPEG) showed high diffraction efficiency (> 90%) under an optimized condition. High diffraction efficiency could be ascribed to the fast diffusion and efficient polymerization of monomers under interference light to generate refractive index modulation. The TSPEG modified photopolymer film could be successfully used for holographic memory.

• Journal of KIISE:Information Networking
• /
• v.32 no.4
• /
• pp.543-550
• /
• 2005

Demand for better services in the Internet has been increasing due to the rapid growth of the Internet, and hence next generation routers are required to perform intelligent packet classification. For a given classifier defining packet attributes or contents, packet classification is the process of identifying the highest priority rule to which a packet conforms. A notable characteristic of real classifiers is that a packet matches only a small number of distinct source-destination prefix pairs. Therefore, a lot of schemes have been proposed to filter rules based on source and destination prefix pairs. However, most of the schemes are based on sequential one-dimensional searches using trio which requires huge memory. In this paper, we proposea memory-efficient two-dimensional search scheme using source and destination prefix pairs. By constructing binary prefix tree, source prefix search and destination prefix search are simultaneously performed in a binary tree. Moreover, the proposed two-dimensional binary prefix tree does not include any empty internal nodes, and hence memory waste of previous trio-based structures is completely eliminated.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.449-457
• /
• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.12
• /
• pp.1177-1187
• /
• 2010

Flash memory becomes popular storage for small devices due to its efficiency, portability, low power consumption and large capacity. Unlike on hard disks, however, write operation on flash memory is much more expensive than read operation, so that it is critical for performance enhancement to reduce the number of executions of write operation. This paper proposes static analysis to rewrite a program to reduce the total number of write operations by merging writable data in a minimum number of pages. To achieve this, we collect information about writable areas by static analysis, and about frequently executed paths by profiling for practicality, and combine both to rewrite the application program to reallocate data. The performance enhancement gained from the proposed methods is shown using a FAST simulator.

• Nuclear Engineering and Technology
• /
• v.48 no.3
• /
• pp.635-641
• /
• 2016

Because of prohibitive data storage requirements in large-scale simulations, the memory problem is an obstacle for Monte Carlo (MC) codes in accomplishing pin-wise three-dimensional (3D) full-core calculations, particularly for whole-core depletion analyses. Various kinds of data are evaluated and quantificational total memory requirements are analyzed based on the Reactor Monte Carlo (RMC) code, showing that tally data, material data, and isotope densities in depletion are three major parts of memory storage. The domain decomposition method is investigated as a means of saving memory, by dividing spatial geometry into domains that are simulated separately by parallel processors. For the validity of particle tracking during transport simulations, particles need to be communicated between domains. In consideration of efficiency, an asynchronous particle communication algorithm is designed and implemented. Furthermore, we couple the domain decomposition method with MC burnup process, under a strategy of utilizing consistent domain partition in both transport and depletion modules. A numerical test of 3D full-core burnup calculations is carried out, indicating that the RMC code, with the domain decomposition method, is capable of pin-wise full-core burnup calculations with millions of depletion regions.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.7_8
• /
• pp.341-351
• /
• 2003

For debugging effectively the shared-memory programs with nested parallelism, it is important to detect efficiently the first races which incur non-deterministic executions of the programs. Previous on-the-fly technique detects the first races in two passes, and shows inefficiencies both in execution time and memory space because the size of an access history for each shared variable depends on the maximum parallelism of program. This paper proposes a new on-the-fly technique to detect the first races in two passes, which is constant in both the number of event comparisons and the space complexity on each access to shared variable because the size of an access history for each shared variable is a small constant. This technique therefore makes on-the-fly race detection more efficient and practical for debugging shared-memory programs with nested parallelism.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.255-255
• /
• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of the Korea Society of Computer and Information
• /
• v.26 no.11
• /
• pp.11-19
• /
• 2021

In this paper, we propose a prototype platform combined with the power management system using, as an auxiliary power storage device, a supercapacitor that can be fast charged and discharged with high power efficiency as well as semi-permanent charge and discharge cycle life. For the proposed platform, we designed a technique which is capable of detecting the state of power cutoff or resumption of power supplied from the solar panel in accordance with physical environment changes through an interrupt attached to the micro-controller was developed. To prevent data loss in a computing environment in which continuous power supply is not guaranteed, we implemented a low-level system software in the micro-controller to transfer program context and data in volatile memory to nonvolatile memory when power supply is cut off. Experimental results shows that supercapacitors effectively supply temporary power as auxiliary power storage devices. Various benchmarks also confirm that power state detection and transfer of program context and data from volatile memory to nonvolatile memory have low overhead.