• The Journal of the Convergence on Culture Technology
• /
• v.9 no.3
• /
• pp.803-809
• /
• 2023

This paper analyzes and evaluates to optimally build a data collection system essential for factory energy management systems on an edge-based lightweight platform. A "Sensor/OPC-UA simulator" was developed based on sensors in an actual food factory and used to evaluate the storage engine of edge devices. The performance of storage engines in edge devices was evaluated to suggest the optimal storage engine. The experimental results show that when using the RocksDB storage engine, it has less than half the memory and database size compared to using InnoDB, and has a 3.01 times faster processing time. This study enables the selection of advantageous storage engines for managing time-series data on devices with limited resources and contributes to further research in this field through the sensor/OPC simulator.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• 2023.05a
• /
• pp.98-99
• /
• 2023

In the maritime digital forensic part, it is very important and difficult process that analysis of data and information with vessel navigation system's binary log data for situation awareness of maritime accident. In recent years, analysis of vessel's navigation system's trajectory information is an essential element of maritime accident investigation. So, we made an experiment about corruption with various memory device in navigation system. The analysis of corruption test in seawater give us important information about the valid pulling time of sunken ship for acquirement useful trajectory information.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.46 no.3
• /
• pp.186-197
• /
• 2023

In this study, we focus on the improvement of data quality transmitted from a weather buoy that guides a route of ships. The buoy has an Internet-of-Thing (IoT) including sensors to collect meteorological data and the buoy's status, and it also has a wireless communication device to send them to the central database in a ground control center and ships nearby. The time interval of data collected by the sensor is irregular, and fault data is often detected. Therefore, this study provides a framework to improve data quality using machine learning models. The normal data pattern is trained by machine learning models, and the trained models detect the fault data from the collected data set of the sensor and adjust them. For determining fault data, interquartile range (IQR) removes the value outside the outlier, and an NGBoost algorithm removes the data above the upper bound and below the lower bound. The removed data is interpolated using NGBoost or long-short term memory (LSTM) algorithm. The performance of the suggested process is evaluated by actual weather buoy data from Korea to improve the quality of 'AIR_TEMPERATURE' data by using other data from the same buoy. The performance of our proposed framework has been validated through computational experiments based on real-world data, confirming its suitability for practical applications in real-world scenarios.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.6
• /
• pp.1299-1306
• /
• 2023

In this paper, we present a system for undesignated cultural heritage management and real-time theft chase, which uses flash-based large-capacity storage. The proposed system is composed of 3 parts, such as a cultural management device, a flash-based server, and a monitoring service for managing cultural heritages and chasing thefts using IoT technologies. However flash-based storage needs methods to overcome the limited lifespan. Therefore, in this paper, we present a system, which uses the disk buffer in flash-based storage to overcome the disadvantage, and evaluate the system performance in various environments. In our experiments, LRU policy shows the number of direct writes in the flash-based storage by 10.7% on average compared with CLOCK and FCFS.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.8 no.4
• /
• pp.599-604
• /
• 1998

We have investigated Pt and $RuO_2$ as a bottom electrode for ferroelectric capacitor applications. The bottom electrodes were prepared by using an RF magnetron sputtering method. Some of the investigated parameters were a substrate temperature, gas flow rate, RF power for the film growth, and post annealing effect. The substrate temperature strongly influenced the surface morphology and resistivity of the bottom electrodes as well as the film crystallographic structure. XRD results on Pt films showed a mixed phase of (111) and (200) peak for the substrate temperature ranged from RT to $200^{\circ}C$, and a preferred (111) orientation for $300^{\circ}C$. From the XRD and AFM results, we recommend the substrate temperature of $300^{\circ}C$ and RF power 80W for the Pt bottom electrode growth. With the variation of an oxygen partial pressure from 0 to 50%, we learned that only Ru metal was grown with 0~5% of $O_2$ gas, mixed phase of Ru and $RuO_2$ for $O_ 2$ partial pressure between 10~40%, and a pure $RuO_2$ phase with $O_2$ partial pressure of 50%. This result indicates that a double layer of $RuO_2/Ru$ can be grown in a process with the modulation of gas flow rate. Double layer structure is expected to reduce the fatigue problem while keeping a low electrical resistivity. As post anneal temperature was increased from RT to $700^{\circ}C$, the resistivity of Pt and $RuO_2$ was decreased linearly. This paper presents the optimized process conditions of the bottom electrodes for memory device applications.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1993.06a
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Applied Microscopy
• /
• v.38 no.4
• /
• pp.279-284
• /
• 2008

The phase change materials have been extensively used as an optical rewritable data storage media utilizing their phase change properties. Recently, the phase change materials have been spotlighted for the application of non-volatile memory device, such as the phase change random access memory. In this work, we have investigated the crystallization behavior and microstructure analysis of In-Sb-Te (IST) thin films deposited by RF magnetron sputtering. Transmission electron microscopy measurement was carried out after the annealing at $300^{\circ}C$, $350^{\circ}C$, $400^{\circ}C$ and $450^{\circ}C$ for 5 min. It was observed that InSb phases change into $In_3SbTe_2$ phases and InTe phases as the temperature increases. It was found that the thickness of thin films was decreased and the grain size was increased by the bright field transmission electron microscopy (BF TEM) images and the selected area electron diffraction (SAED) patterns. In a high resolution transmission electron microscopy (HRTEM) study, it shows that $350^{\circ}C$-annealed InSb phases have {111} facet because the surface energy of a {111} close-packed plane is the lowest in FCC crystals. When the film was heated up to $400^{\circ}C$, $In_3SbTe_2$ grains have coherent micro-twins with {111} mirror plane, and they are healed annealing at $450^{\circ}C$. From the HRTEM, InTe phase separation was occurred in this stage. It can be found that $In_3SbTe_2$ forms in the crystallization process as composition of the film near stoichiometric composition, while InTe phase separation may take place as the composition deviates from $In_3SbTe_2$.

• Nuclear Medicine and Molecular Imaging
• /
• v.43 no.5
• /
• pp.459-467
• /
• 2009

Purpose: The maximum likelihood-expectation maximization (ML-EM) is the statistical reconstruction algorithm derived from probabilistic model of the emission and detection processes. Although the ML-EM has many advantages in accuracy and utility, the use of the ML-EM is limited due to the computational burden of iterating processing on a CPU (central processing unit). In this study, we developed a parallel computing technique on GPU (graphic processing unit) for ML-EM algorithm. Materials and Methods: Using Geforce 9800 GTX+ graphic card and CUDA (compute unified device architecture) the projection and backprojection in ML-EM algorithm were parallelized by NVIDIA's technology. The time delay on computations for projection, errors between measured and estimated data and backprojection in an iteration were measured. Total time included the latency in data transmission between RAM and GPU memory. Results: The total computation time of the CPU- and GPU-based ML-EM with 32 iterations were 3.83 and 0.26 see, respectively. In this case, the computing speed was improved about 15 times on GPU. When the number of iterations increased into 1024, the CPU- and GPU-based computing took totally 18 min and 8 see, respectively. The improvement was about 135 times and was caused by delay on CPU-based computing after certain iterations. On the other hand, the GPU-based computation provided very small variation on time delay per iteration due to use of shared memory. Conclusion: The GPU-based parallel computation for ML-EM improved significantly the computing speed and stability. The developed GPU-based ML-EM algorithm could be easily modified for some other imaging geometries.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.37 no.2
• /
• pp.1-14
• /
• 2000

The rosette-scan seeker, mounted on the infrared guided missile, is a device that tracks the target It can acquire the 2D image of the target by scanning a space about target in rosette pattern with a single detector Since the detected image is changed according to the position of the object in the field of view and the number of the object is not fixed, the unsupervised methods are employed in clustering it The conventional ISODATA method clusters the objects by using the distance between the seed points and pixels So, the clustering result varies in accordance with the shape of the object or the values of the merging and splitting parameters In this paper, we propose an Array Linkage Clustering Algorithm (ALCA) as a new clustering algorithm improving the conventional method The ALCA has no need for the initial seed points and the merging and splitting parameters since it clusters the object using the connectivity of the array number of the memory stored the pixel Therefore, the ALCA can cluster the object regardless of its shape With the clustering results using the conventional method and the proposed one, we confirm that our method is better than the conventional one in terms of the clustering performance We simulate the rosette scanning infrared seeker (RSIS) using the proposed ALCA as an infrared counter countermeasure The simulation results show that the RSIS using our method is better than the conventional one in terms of the tracking performance.

• Korean Chemical Engineering Research
• /
• v.47 no.6
• /
• pp.715-719
• /
• 2009

The phase change electrode board for the bio-information detection through electrical property response of phase change material was developed in this study. We manufactured the electrode board using Aluminum first that is widely used in conventional semiconductor device process. Without further treatment, these aluminum electrodes tend to contain voids in PETEOS(plasma enhanced tetraethyoxysilane) material that are easily detected by cross-sectional SEM(Scanning Electron Microscope). The voids can be easily attacked and transformed into holes in between PETEOS and electrodes after etch back and washing process. In order to resolve this issue of Al electrode board, we developed a electrode board manufacturing method using low resistivity TiN, which has advantages in terms of the step-coverage of phase change($Ge_2Sb_2Te_5$, GST) thin film as well as thermodynamic stability, without etch back and washing process. This TiN material serves as the top and bottom electrode in PRAM(Phase-change Random Access Memory). The good connection between the TiN electrode and GST thin film was confirmed by observing the cross-section of TiN electrode board using SEM. The resistances of amorphous and crystalline GST thin film on TiN electrodes were also measured, and 1000 times difference between the amorphous and crystalline resistance of GST thin film was obtained, which is well enough for the signal detection.