• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.162-164
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• 2012

In this study, we fabricate Pt nanoparticle (NP)-embedded MOS capacitors at room temperature and investigate their memory characteristics. The Pt NPs are separated from each other and situated between the tunnel and control oxide layers. The average size and density of the Pt NPs are 4 nm and $3.2{\times}10^{12}cm^{-2}$, respectively. Counterclockwise hysteresis with a width of 3.3 V is observed in the high-frequency capacitance-voltage curve of the Pt NP-embedded MOS capacitor. Moreover, more than 93% of the charge remains even after $10^4$ s.

• Transactions of the Society of Information Storage Systems
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• v.2 no.1
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• pp.71-78
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• 2006

In this work, we propose a new type of HDD Load/Unload(L/UL) suspension featuring shape memory alloy(SMA). The mechanical and thermal properties of the SMA film with respect to the material phase states are experimentally estimated and the SMA film is carefully integrated to the suspension. In order to obtain the desirable dynamic characteristics of the suspension during L/UL process, the design parameters of the SMA film such as geometric properties are determined by considering the vibration modes of the suspension related to the L/UL performance. After analyzing the modal characteristics of the proposed suspension, L/UL performance is evaluated through L/UL simulation by observing the vibration motion and minimum flying height of the slider during L/UL process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Korean Journal of Cognitive Science
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• v.35 no.1
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• pp.1-21
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• 2024

This study investigates the characteristics of visual working memory (VWM) representations by examining two theoretical models: the integrated-object and the parallel-independent feature storage models. Experiment I involved a change detection task where participants memorized arrays of either orientation bars, colored squares, or both. In the one-feature condition, the memory array consisted of one feature (either orientations or colors), whereas the two-feature condition included both. We found no differences in change detection performance between the conditions, favoring the integrated object model over the parallel-independent feature storage model. Experiment II employed a recall task with memory arrays of isosceles triangles' orientations, colored squares, or both, and one-feature and two-feature conditions were compared for their recall performance. We found again no clear difference in recall accuracy between the conditions, but the results of analyses for memory precision and guessing responses indicated the weak object model over the strong object model. For ongoing debates surrounding VWM's representational characteristics, these findings highlight the dominance of the integrated object model over the parallel independent feature storage model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• Journal of Korea Foundry Society
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• v.28 no.1
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• pp.31-36
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• 2008

Ti-Ni-Cu alloys are very attractive shape memory alloys for applications as actuators because of a large transformation elongation and a small transformation hysteresis. Rapidly solidified Ti-Ni alloy ribbons have been known to have the shape memory effect and superelasticity superior to the alloy ingots fabricated by conventional casting. In this study, solidification structures and shape memory characteristics of $Ti-Ni_{30}-Cu_{20}$ alloy ribbons prepared by melt spinning were investigated by means of DSC and XRD. Operating parameters to fabricate the amorphous ribbons were the wheel velocity of 55 m/s and the melt spinning temperature of $1500^{\circ}C$. The crystallization temperature was measured to be $440^{\circ}C$. The crystallized ribbons exhibited very fine microstructure after annealing at $440^{\circ}C$ for 10 minutes and $460^{\circ}C$ for 5 minutes and was deformed up to about 6.8% and 6.23% in ductile manner, respectively. Stress-strain curve of the ribbon exhibited a flat stress-plateau at 64 MPa and this is associated with the stress-induced a B2-B19 martensitic transformation. During cycle deformation with the applied stress of 220 MPa, transformation hysteresis and elongation associated with the B2-B19 transformation were observed to be $4.3^{\circ}C$ and 3.6%.

• Transactions on Electrical and Electronic Materials
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• v.8 no.2
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• pp.73-78
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• 2007

The crystallization temperature in GeTe solid electrolyte films was improved by in situ-nitrogen doping by rf magnetron co-sputtering technique at room temperature. The crystallization temperature of $250\;^{\circ}C$ in electrolyte films without nitrogen doping increased by approximately $300\;^{\circ}C$, $350\;^{\circ}C$, and above $400\;^{\circ}C$ in films deposited with nitrogen/argon flow ratios of 10, 20, and 30 %, respectively. A PMC memory device with $Ge_{45}Te_{55}$ solid electrolytes deposited with nitrogen/argon flow ratios of 20 % shows reproducible memory switching characteristics based on resistive switching at threshold voltage of 1.2 V with high $R_{off}/R_{on}$ ratios. Nitrogen doping into the silver saturated GeTe electrolyte films improves the crystallization temperature of electrolyte films and does not appear to have a negative impact on the switching characteristics of PMC memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.136-137
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• 2007

In this study, a single ZnO nanowire - CdTe nanoparticle nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of ZnO nanowire-based field effect transistor (FET) devices with CdTe nanoparticles embedded in the $Al_2O_3$ gate materials and without the CdTe nanoparticles.