• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.1275-1281
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• 2011

Most of the railway traffic control systems are using in the DBMS(Database Management System)is a disk-based DBMS. When the train schedule and the event data is inputted and referred at real time on Disk-based DBMS, it is characteristic of the slow access time and the data is preserved permanently. For this reason, this paper suggests the way of improving for Railway Traffic Control System by the hybrid DBMS using a combination of memory and disk. We apply the Hybrid DBMS to Railway Traffic Control System and compare the existing method with suggested one using the same data. As a result of comparison, we have come to the conclusion that suggested method is far more performance to shorten data access time and process a mass information than the previous methods.

• 한국정보과학회논문지:시스템및이론
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• 제37권3호
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• pp.172-183
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• 2010

가상 메모리 시스템(VM)에서 페이지 부재로 발생하는 디스크 I/O를 감소시키기 위해 페이지 선반입 기법을 사용한다. 이 기법은 부재 페이지와 함께 추가적인 페이지들을 한 번의 디스크 I/O로 미리 읽는다. 그런데, 4.4BSD와 같은 운영체제의 VM은 응용 프로그램의 페이지 참조 패턴을 고려하지 않고 항상 가능한 많은 페이지들을 선반입하고자 한다. 이 방법은 선반입된 페이지들 중 일부만 사용하는 참조패턴에서 디스크 참조 시간을 증가시키며, 유용한 페이지들을 메모리에서 내보내는 메모리 오염을 야기한다. 이런 문제를 해결하기 위해 본 논문은 적응적 페이지 선반입 제어 기법(APC)을 제안한다. APC는 선반입 페이지들 중에서 메모리에 존재하는 동안 참조된 페이지들의 비율을 프로세스 단위로 주기적으로 측정하고, 이 비율을 사용하여 4.4BSD VM이 선반입하고자 하는 페이지의 개수를 조절한다. 그래서 실행도중 페이지 참조 패턴이 바뀌더라도 적절한 수의 페이지를 선반입할 수 있다. 성능 검증을 위해 APC를 4.4BSD 기반의 FreeBSD 6.2에 구현하였으며, SOR, SMM, FFT 벤치마크를 통해 성능을 측정하였다. 성능 측정 결과 APC는 기존 BSD VM보다 벤치마크의 실행 시간을 최대 57% 단축하였다.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.269-277
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• 2018

NAND flash memory has widely been used because of non-volatility, low power consumption and fast access time. However, it suffers from inability to provide update-in-place and the erase cycle is limited. The unit of read/write operation is a page and the unit of erase operation is a block. Moreover erase operation is slower than other operations. We proposed the Adaptive Garbage Collection (called "AGC") policy which focuses on not only reducing garbage collection process time for real-time guarantee but also wear-leveling for a flash memory lifetime. The AGC performs better than Cost-benefit policy and Greedy policy. But the AGC does not consider the operation characteristics. So we proposed the Advanced Adaptive Garbage Collection (called "A-AGC") policy which considers the page write operation count and block erase operation count. The A-AGC reduces the write operations by considering the data update frequency and update data size. Also, it reduces the erase operations by considering the file fragmentation. We implemented the A-AGC policy and measured the performance compared with the AGC policy. Simulation results show that the A-AGC policy performs better than AGC, specially for append operation.

• 통합자연과학논문집
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• 제14권4호
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• pp.189-196
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• 2021

Recently, as a countermeasure for cyber breach attacks and confidential leak incidents on PC hard disk memory storage data of the metaverse industry, it is required when reviewing and developing a remote-based regular/real-time monitoring and analysis security system. The reason for this is that more than 90% of information security leaks occur on edge-end PCs, and tangible and intangible damage, such as an average of 1.20 billion won per metaverse industrial security secret leak (the most important facts and numerical statistics related to 2018 security, 10.2018. the same time as responding to the root of the occurrence of IT WORLD on the 16th, as it becomes the target of malicious code attacks that occur in areas such as the network system web due to interworking integration when building IT infrastructure, Deep-Access-based regular/real-time remote. The concept of memory analysis and audit system is key.

• Journal of Positioning, Navigation, and Timing
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• 제12권1호
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• pp.75-81
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• 2023

In this study, we design an optimized Graphics Processing Unit (GPU)-based GNSS signal processing technique with the goal of designing and implementing a GNSS Software Defined Receiver (SDR) that can operate in real time all-in-view mode under multi-constellation and multi-frequency signal environment. In the proposed structure the correlators of the existing GNSS SDR are processed by the GPU. We designed a memory structure and processing method that can minimize memory access bottlenecks and optimize the GPU memory resource distribution. The designed GNSS SDR can select and operate only the desired GNSS or desired satellite signals by user input. Also, parameters such as the number of quantization bits, sampling rate, and number of signal tracking arms can be selected. The computing capability of the designed GPU-based GNSS SDR was evaluated and it was confirmed that up to 2400 channels can be processed in real time. As a result, the GPU-based GNSS SDR has sufficient performance to operate in real-time all-in-view mode. In future studies, it will be used for more diverse GNSS signal processing and will be applied to multipath effect analysis using more tracking arms.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• 한국통신학회논문지
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• 제12권1호
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• pp.50-59
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• 1987

많은 production rule(혹은 간단히 production)로부터 현 상태에 만족되는 rule을 빨리 찾아내기 위하여 현재까지는 RAM(Ramdom Access Memory)에 탕을 둔 필터(filter)사용등의 여러 방법에 제시되었으나, 본 연구에서는 보다 효율적인 CAM(Content Addressable Memory)의 이용을 제시하고, 이를 위해 CAM의 각 bit에 따라, 용도에 다른 구분 및 데이터 구조를 설계하고, 이를 컴퓨터 시뮬레이션을 통해 기존 RAM을 사용했을 경우와 비교하였다.

• Journal of Information Technology Applications and Management
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• 제12권4호
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• pp.59-70
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• 2005

Flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. in order to achieve this goal, we devise a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing. F2Pl improves transaction performance by allowing multi version reads and efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional scheme.

• Journal of the Optical Society of Korea
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• 제18권6호
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• pp.698-705
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• 2014

We propose a new development for calculating a computer-generated hologram (CGH) through the use of multiple general-purpose graphics processing units (GPGPUs). For optimization of the implementation, CGH parallelization, object point tiling, memory selection for object point, hologram tiling, CGMA (compute to global memory access) ratio by block size, and memory mapping were considered. The proposed CGH was equipped with a digital holographic video system consisting of a camera system for capturing images (object points) and CPU/GPGPU software (S/W) for various image processing activities. The proposed system can generate about 37 full HD holograms per second using about 6K object points.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.