• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.137-144
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• 2008

In this paper, a novel voltage-controlled oscillator(VCO) using the output matching network based on the harmonic control circuit is presented for improving the phase noise property. The phase noise suppression is achieved through the harmonic control circuit having the short impedances for both second-harmonic and third-harmonic components, which has been connected at the output matching network. Also, we have used the microstrip square open loop multiple split-ring resonator(OLMSRR) having the high-Q property to further reduce the phase noise of VCO. Because the output matching network based on the harmonic control circuit has been used for reducing the phase noise property instead of the High-Q resonator, we can obtain the broad tuning range by the low-Q resonator. The phase noise of the proposed VCO using the output matching network based on the harmonic control circuit and the microstrip square OLMSRR has been $-127.5{\sim}126.33$ dBc/Hz @ 100 kHz in the tuning range, $5.744{\sim}5.839$ GHz. Compared with the reference VCO using the output matching network without the harmonic control circuit and the microstrip line resonator, the phase noise property of the proposed VCO has been improved in 26.66 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1358-1363
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• 2012

This paper deals with the analysis of high efficiency small antenna like superconductor antenna. The superconductor antenna is useful to low frequency range because surface resistance of superconductor increased with the rate of square of frequency. Thus, the used antenna increases in size. For such a reason, the role of the matching circuit is very important in small antenna. In this paper, low loss antenna included the optimal structure of matching circuit is analyzed by using quasi-static approximation. To verify the results of this paper, input impedance and radiation characteristics of this antenna have been evaluated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.141-146
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• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.1
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• pp.1-7
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• 2019

In this paper, a design technique using a bypass capacitor is proposed to improve the antenna efficiency of an inverted-F antenna (IFA) with a band stop matching circuit (BSMC). The proposed antenna operates in the LTE bands 26 and 5(814~ 894 MHz). The bandwidth of the IFA is expanded from 803~863 MHz to 800~888 MHz using the impedance change caused by the BSMC. To enhance the antenna efficiency in the expanded frequency band, the bypass capacitor is applied to the IFA with the BSMC. The bypass capacitor improves the efficiency of the antenna by reducing the current variation of the IFA with the BSMC. The proposed antenna has a bandwidth of 804~895 MHz and the antenna efficiency increases by more than 10 % in the extended frequency band by using the bypass capacitor.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.569-575
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• 2014

A highly efficient class E power amplifier is demonstrated for application to wireless power transfer system. The amplifier is designed with an L-type matching at the output for harmonic rejection and output matching. The power loss and the effect of each component in the amplifier with the matching circuit are analyzed with the current ratio transmitted to the output load. Inductors with a quality factor of more than 120 are used in a dc feed and the matching circuit to improve transmission efficiency. The single-ended amplifier with 20 V supply voltage shows 7.7 W output power and 90.8% power added efficiency at 6.78 MHz. The wireless power transfer (WPT) system with the amplifier shows 5.4 W transmitted power and 82.3% overall efficiency. The analysis and measurements show that high-Q inductors are required for the amplifier design to realize highly efficient WPT system.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1001-1004
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• 2000

RFID system is applied to identify, locate and track people, cars, animals. In RFID system, the passive transponder without battery has some benefits than active transponder, such as no restriction in battery exchange and in battery’s life. But it needs auxiliary RF-DC conversion circuit. RF-DC conversion circuit originated from Wireless Power Transmission (WPT). In this paper, RF-DC conversion circuit consists of a microstrip patch antenna and impedance matching circuit, Cock-croft Walton circuit. And RF-DC conversion circuits have two kinds of T-type and Cross-type impedance matching circuits.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.12
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• pp.560-566
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• 1986

In the design of an RF discharge system, the electrical equivalence of the gas discharge must be known. With this knowledge, one can design a suitable matching network for a maximum power transfer from the RF generator into the discharge. For this purpose, an experiment has been conducted in which the electrical impedance (conductance and capacitance) was determined as a function of power. In parallel with this, a detailed theoretical analysis has been done and the results are in accord with those of our experiment. Design equations are also given for a simple matching network, and a design example is presented to demonstrate its application. During the actual operation of an RF discharge system, however, it has been often observed that the reflected power tends to vary in small values due to the changes in the impedance of the system. This problem can be relieved by adding an automatic impedance matching circuit to the system and this paper presents such an automatic impedance matching network.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3208-3229
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• 2017

Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.615-618
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• 2006

The broadband power detector for direct- onversion Six-port output circuit was designed and implementaed in this paper. The power detector should linearly operated to produce the linear amplitude and phase signal fer input RF signal in required broadband. So, the power detector should be designed under conditions of matching circuit with low VSWR. The designed power detectors, which were implemented in L-band with 50 ohm matching and Ku-band with matching circuit and isolator, respectively, were evaluated in the performances.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.529-532
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• 1988

This paper proposes a graph matching algorithm based on simulated annealing, which assures the globally optimal solution for circuit partitioning for the placement in the rectilinear region occurring as a result of the pre-placement of some macro cells, or onto the nonplanar surface in some military or space applications. The circuit graph ($G_{C}$) denoting the circuit topology is formed by a hierarchical bottom-up clustering of cells, while another graph called region graph ($G_{R}$) represents the geometry of a planar rectilinear region or a nonplanar surface for circuit placement. Finding the optimal many-to-one vertex mapping function from $G_{C}$ to $G_{R}$, such that the total mismatch cost between two graphs is minimal, is a combinatorial optimization problem which was solved in this work for various examples using simulated annealing.