• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1221-1230
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• 1997

In this study, the performance of a parallel file system(N-PFS), which is inplemented using conventional disks as disk arrays on a Workstation Cluster, is analyzed by using analytical method and adtual values in experiments.N-PFS can be used as high-performance file sever in small-scale server systems and effciently pro-cess massive data I/Os such as multimedia and scientifid data. In this paper, an analytical model was suggested and the correctness of the suggested was verified by analyzing the experimental values on a system.The result of the appropriate stping unit for processing massive data of the Workstation Cluster with 8 disks is 64-128Kbytes and the maximum throughput on it is 15.8 Mbytes/ses.In addition, the performance of parallel file system on massive data is bounded by the time required to copy data between buffers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.11
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• pp.1201-1209
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• 1991

Generally, the conventional tracking algorithms are very limited in the practical applications because of its exponential increase in the required computation time for the number of targets being tracked. Therefore, in this paper, a new real-time moving target tracking system is proposed, which is based on the neural networks with massive parallel processing capabilities. Through the theoretical and experimental results, the target tracking system based on neural network algorithm is analyzed to be computationally independent of the number of objects being tracked and performs the optimized tracking through its massive parallel computation and learning capabilities. And this system also has massive matched filtering effects because the moving target data can be compactly stored in the interconnection weights by learning. Accordingly, a possibility of the proposed neural network target tracking system can be suggested to the fields of real-time application.

• Journal of Computing Science and Engineering
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• v.7 no.3
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• pp.147-158
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• 2013

This invited paper introduces results on Web science and technology obtained during work with the Korea Advanced Institute of Science and Technology. In the first part, we discuss algorithms for exploring the deep Web, which refers to the collection of Web pages that cannot be reached by conventional Web crawlers. In the second part, we discuss sorting algorithms on the MapReduce system, which has become a dominant paradigm for massive parallel computing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.607-610
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• 2007

In this paper, proposes the monitoring system it will be able to trace the executed of each threads in OpenMP based a parallel program. The monitoring system of existing in uses each threads label information and the analysis technique which uses the access-history was most. This has the problem which raises the time and space complexity which is caused by with massive information creation. In this paper, only the thread which includes interest information it creates tracking information with the target. And it provides information which is intuitive to the user it provides the visualization system for to a same time. The visualization model is composed the images-information of a base. This does to be it will be able to understandable a program execute situation using an image processing technique. Therefore, this paper provides the parallel program an effective debugging environment.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.

• Journal of Practical Engineering Education
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• v.5 no.2
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• pp.163-168
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• 2013

The vicious cycle of over-education has been made. That is, higher education enrollment rate is high, but university graduate employment rate is low. To eliminate this cycle and relieve youth unemployment and young people to enter the labor market early, dual education and training system is needed. This dual system can support working and learning in parallel. So, worker can get the opportunity pre-employment and post-learning and improve his/her job skills. Recent MOOC (Massive Open On-line Course), a new form of online education system, has emerged. MOOC combines education, entertainment and social networking, and emphasize the interaction between faculty and student and between students. The educational contents of MOOC are available free of charge. Using newly changed online education environments we can effectively provide knowledge and skills. In technology and engineering education hands-on training is necessary. In order to support work based learning dual system for worker to work and learn in parallel, we should build the multi-learning system to combine the online education and campus hands-on practice.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.6-10
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• 2017

Recent enhancement in the still image acquisition devices has been widely perpetrated into the daily life of the common people. Due to this trend, the voluminous still images, that are produced and shared in the personal or the massive storage, need to controlled with effective and efficient management. The human-devised or system-generated still image identifiers used for the identification of the images are at risk in the situation of unexpected changing or eliminating of the identifiers. In this paper, we propose a parallel processing based method for still image identifier generation by utilizing the still image internal features.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.20-24
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• 2006

In this paper, our research efforts and activities for displaying flight simulation graphics on multi-monitors connected to a Linux cluster is introduced. In this pilot system graphics rendering as well as view calculation including LOD implementation for each monitor is peformed on each sub-node computer connected to the monitor rather than using an expensive main server. The Linux cluster is constructed by combining general-purpose desktop computers, and MPI library Is used for communication between sub-nodes. It could be concluded from our experience that it is possible to construct a massive multi-monitor display system by adding to the cluster as many sub-node computers and monitors as possible with economic efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.