• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.4
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• pp.174-186
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• 2004

Striations are growth-induced inhomogeneities which hamper the applications of solid-solution crystals and of doped crystals in numerous technologies. Thus the optimized performance of solid solutions often can not be exploited. The inhomogeneity problem can be solved in specific cases by achieving a distribution coefficient one in growth from melts and from solutions. Macrostep-induced striations can be suppressed by controlling the growth mode, by achieving growth on facets thereby preventing step bunching. Thermal striations are commonly assumed to be caused by convective instabilities so that reduced convection by microgravity or by damping magnetic fields was and is widely attempted to reduce such inhomogeneities. Here it will be shown that temperature fluctuations at the growth interface cause striations, and that hydrodynamic fluctuations in a quasi-isothermal growth system do not cause striations. The theoretically derived conditions were experimentally established and allowed the growth of striation-free crystals of $KTa_{1-x}Nb_xO_3$"KTN" solid solutions. Hydrodynamic variations from the accelerated crucible rotation technique ACRT did not cause striations as long as the temperature was controlled within $0.03^{\circ}$ at $1200^{\circ}C$ growth temperature. Alternative approaches to solve or reduce the segregation and striation problems in growth from melts and from solutions are discussed as well.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.19-37
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• 1996

Scanning electron microscopy (SEM) has been applied to observe directly the {{{{ SQRT { 19} }}}}${\times}${{{{ SQRT { 19} }}}} and (1${\times}$1)HT reconstructions and the transition associated step bunching on the GaAs (111)B surfaces under As pressure. Close to the transition point, {{{{ SQRT { 19} }}}}${\times}${{{{ SQRT { 19} }}}}an d (1${\times}$1)HT reconstructions are observed in dark and bright domains by SEM and determined by micro-probe reflection high-energy electron diffraction (${\mu}$-RHEED). The reconstruction diagram shows hyster-esis. The stepped surface morphology during the reconstruction transition was unstable. Heavy step bunching with rough macrostep edges was observed.

• Journal of Surface Science and Engineering
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• v.16 no.4
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• pp.173-187
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• 1983

Zinc was electrodeposited at temperature from 20$^{\circ}C$ to 60$^{\circ}C$ over the ranges of the current density from 2 to 20 A/dm2 in acid chloride bath. The cathode overpotentials increased with increasing current density and decreasing tem-perature. The (10$.$3)-(10$.$2) preferred orientation developed at cathode overpotentials below about 450mV, the (10$.$3)(10$.$2)-(10$.$1) texture developed at overpotentials between 500mV and 950mV, and the (00$.$1) (10$.$3) texture developed at cathode overpotentials about 1000mV. The (00$.$1) (10$.$3) preferred orientation was also formed at the lower potentials between 400mV and 850mV at temperatures above 40$^{\circ}C$. The preferred orientations of the zinc deposits was discussed was discussed with both cathode overpo-tential and surface energy of deposit lattice planes. The pyramid type of structure with macrostep developed at low cathode overpotentials and the truncated pyramidal type developed at higher overpotenial.