• Proceedings of the KIPE Conference
• /
• 2001.10a
• /
• pp.683-686
• /
• 2001

This paper presents a novel prototype of the utility­interactive voltage source type sinewave pulse modulated power inverter using a high-frequency flyback transformer link. The proposed power conditioner circuit for the solar photovoltaic generation and small scale fuel cell has an isolation function due to the safety of the power processing system, which is more cost effective and acceptable for the small-scale distributed renewal energy conditioning and processing systems. The discontinuous current mode(DCM) of this power processing conversion circuit is applied to implement a simple circuit topology and pulse modulated control scheme. Its operation principle is described on the basis of simulation evaluations and theoretical considerations. The simulation results obtained herein prove that the proposed inverter outputs with sinusoidal waveforms and unity power factor currents are synchronized to the main voltage in utility power source grid. In this paper, the soft switching topology of high­frequency linked sinewave pulse modulation inverter is proposed and discussed.

• Journal of Power Electronics
• /
• v.15 no.1
• /
• pp.256-267
• /
• 2015

Grid-connected transformerless photovoltaic (PV) inverters (TPVIs) are increasingly dominating the market due to their higher efficiency, lower cost, lighter weight, and reduced size when compared to their transformer based counterparts. However, due to the lack of galvanic isolation in the low voltage grid interconnections of these inverters, the PV systems become vulnerable to leakage currents flowing through the grounded star point of the distribution transformer, the earth, and the distributed parasitic capacitance of the PV modules. These leakage currents are prohibitive, since they constitute an issue for safety, reliability, protection coordination, electromagnetic compatibility, and module lifetime. This paper investigates a wide range of multi-kW range power rating TPVI topologies and classifies them in terms of their leakage current attributes. This systematic classification places most topologies under a small number of classes with basic leakage current attributes. Thus, understanding and evaluating these topologies becomes an easy task. In addition, based on these observations, new topologies with reduced leakage current characteristics are proposed in this paper. Furthermore, the important efficiency and cost determining characteristics of converters are studied to allow design engineers to include cost and efficiency as deciding factors in selecting a converter topology for PV applications.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.13 no.8
• /
• pp.4041-4059
• /
• 2019

Key establishment method based on channel reciprocity for time division duplex (TDD) system has earned a vital consideration in the majority of recent research. While most of the cellular systems rely on frequency division duplex (FDD) systems, especially the 5G network, which is not characterized by the channel reciprocity feature. This paper realizes the generation of a group secret key for multi-terminals communicated through a wireless network in FDD mode, by utilizing the nature of the physical layer for the wireless links between them. I consider a new group key generation approach, which using bitwise XOR with a modified pairwise secret key generation approach not based on the channel reciprocity feature. Precisely, this multi-node secret key agreement technique designed for three wireless network topologies: 1) the triangle topology, 2) the multi-terminal star topology, and 3) the multi-node chain topology. Three multi-node secret key agreement protocols suggest for these wireless communication topologies in FDD mode, respectively. I determine the upper bound for the generation rate of the secret key shared among multi-node, for the three multi-terminals topologies, and give numerical cases to expose the achievement of my offered technique.

• Transactions of Materials Processing
• /
• v.31 no.5
• /
• pp.302-308
• /
• 2022

In this study, the weight of the platen was reduced using the structural strength analysis and topology optimization design of the extruder by finite element analysis. The main components of the extruder such as the stem and billet, were modeled, and the maximum stress and safety factor were verified through structural strength analysis. Based on the results of the structural strength analysis, the optimal phase that satisfies the limitation given to the design area of the structure and maximizes or minimizes the objective function was obtained through a numerical method. The platen was redesigned with a phase-optimal shape, the weight was reduced by 40% (from the initial weight of 11.1 tons to 6.6 tons), and the maximum stress was 147.49 MPa safety factor of 1.86.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.10
• /
• pp.2043-2052
• /
• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• Journal of KIISE:Information Networking
• /
• v.28 no.2
• /
• pp.229-235
• /
• 2001

With the explosive popularity of the World Wide Web, the low penonnance of network often leads web clients to wait a long time for web server's response. To resolve this problem, web caching (proxy) has been considered as the most efficient technique for web server to handle this problem. The placement of web proxy is critical to the overall penonnance, and Li et al. showed the optimal placement of proxies for a web server in the internet with the linear and tree topology when the number of proxies, ]M, is given [4, 5]. They focused on minimizing the over all access time. However, it is also considerable for target web server to minimize the total number of proxies while each proxy server guarantees not to exceed certain res(Xlnse time for each request from its clients. In this paper, we consider the problem of finding the optimal number and placement of web proxies with the lin~ar and tree topology under the given threshold cost for delay time.

• Structural Engineering and Mechanics
• /
• v.56 no.4
• /
• pp.667-694
• /
• 2015

The suspended dome system is a new structural form that has become popular in the construction of long-span roof structures. Suspended dome is a kind of new pre-stressed space grid structure that has complex mechanical characteristics. In this paper, an optimum topology design algorithm is performed using the enhanced colliding bodies optimization (ECBO) method. The length of the strut, the cable initial strain, the cross-sectional area of the cables and the cross-sectional size of steel elements are adopted as design variables and the minimum volume of each dome is taken as the objective function. The topology optimization on lamella dome is performed by considering the type of the joint connections to determine the optimum number of rings, the optimum number of joints in each ring, the optimum height of crown and tubular sections of these domes. A simple procedure is provided to determine the configuration of the dome. This procedure includes calculating the joint coordinates and steel elements and cables constructions. The design constraints are implemented according to the provision of LRFD-AISC (Load and Resistance Factor Design-American Institute of Steel Constitution). This paper explores the efficiency of lamella dome with pin-joint and rigid-joint connections and compares them to investigate the performance of these domes under wind (according to the ASCE 7-05), dead and snow loading conditions. Then, a suspended dome with pin-joint single-layer reticulated shell and a suspended dome with rigid-joint single-layer reticulated shell are discussed. Optimization is performed via ECBO algorithm to demonstrate the effectiveness and robustness of the ECBO in creating optimal design for suspended domes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.181-184
• /
• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Spatial Information Research
• /
• v.17 no.1
• /
• pp.89-102
• /
• 2009

The information of ocean topology is the fundamental source which is necessary for understanding the ocean, producing nautical charts and delimiting maritime boundaries. An echo sounder is being used generally to collect undersea bathymetric data, but an indirect method such as geophysical data acquired by satellites is being used recently. In this study, the outputs of ocean surveying for the production of the Basic Maps of the Sea in 1996 and 1997 in the East Sea and the bathymetric data produced by geophysical data are compared and analyzed. The study areas are Ulleung Plateau, Ulleung Basin and the southern area of Ulleung Basin which have different geophysical characteristics. Through this study, we found that the bathymetric data acquired by an indirect method using satellite is similar to the field surveying results in general configuration of ocean floor and average depth. However, the minimum square error is about 100m in 1700m depth, and it has been observed a local error up to 1000m. In addition, it has been found that the detailed undulation of ocean topology is shown on the gravity data which is acquired by the research vessel.