• Journal of Korea Society of Digital Industry and Information Management
• /
• v.9 no.1
• /
• pp.53-58
• /
• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.210-216
• /
• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.426-432
• /
• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.549-551
• /
• 2005

Bidirectional DC/DC converters allows transfer of power between two dc sources, in either direction. Due to their ability to reverse the direction of flow of power, they are being increasingly used in many applications such as battery charger/dischargers, dc uninterruptible power supplies, electrical vehicle motor drives, aerospace power systems, telecom power supplies, etc. This paper proposes a new bidirectional Sepic/zeta converter. It has low swicthing loss and low conduction loss due to auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of positive and buck/boost-like DC voltage transfer function(M=D/1-D), the proposed converter is very desirable for use in distributed power system . The proposed converter also has both transformerless version and transformer one.

• Proceedings of the KIEE Conference
• /
• 2000.07b
• /
• pp.961-963
• /
• 2000

Most of the application standard of the low-voltage devices have applied one the IEC standard another the UL standard. European union applied the IEC60947-1 standard has not exceed 1000V a.c. or 1500V d.c.. Therefore. it is necessary to the low-voltage device has expended for rated operational voltage with our products. The export of European market shall be made for the CE-Marking in accordance with IEC60947-1 ( Low-voltage switchgear and controlgear). We shall be considered for the requirement with the IEC standard. In this time to study for power supply system at EU ( European union. At that time for design and development in order to the construction and test method among the study for the rated insulation voltage at less then 690V.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.169-172
• /
• 2002

A protection integrated circuit which enables the stable operation of the rechargeable battery should be designed with a low-power architecture because it consumes the power of the battery. This paper proposed a low-power scheme especially when the several series-connected batteries are provided. By adopting a time sharing control of the batteries, the chip size and power consumption could be reduced.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.851-854
• /
• 2003

The low power motion estimation for MPEG-4 is a soft-core for hardwired motion estimation block in MPEG-4. This motion estimation is modified by 10 difference mode. So, this motion estimation decrease a power consumption compare conventional step search. This modified 4SS Low power Motion Estimation has been tested and verified to be valid for implementation of FPGA. The average PSNR between the original image and the motion-compensated image is 28.25dB. And Power consumption is 26mW.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.1
• /
• pp.90-94
• /
• 2013

A low loss power dividing switch in a indoor microwave power distribution system is proposed and designed with a various power dividing ratio. Switching characteristics are analyzed by use of the S-parameter of the switch. Newly proposed switch showed a very low return loss less than -30dB at the operating frequency of 2.45GHz. Three kinds of the switch in which we take out individually 1/2, 1/3 and 1/4 of the input power were fabricated, and measured the delivered, transmitted, and return loss power ratio. Simulated results showed that the lower power ratio is, the better accurate operating performance shows. This switch can switch the input power from 4.5% to 58% with the variance of 5% output power. The experimental results are in good agreement with the simulation within the return loss of 1%.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.11
• /
• pp.2281-2285
• /
• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.7
• /
• pp.110-120
• /
• 2016

A power-efficient neuromodulator is needed for implantable systems. In spite of their stimulation signal's simplicity of wave shape and waiting time of MCU(micro controller unit) much longer than execution time, there is no consideration for low-power design. In this paper, we propose a novel of low-power algorithm based on the characteristics of stimulation signals. Then, we designed and implement a neuromodulation software that we call NMS(neuro modulation simulation). In order to implement low-power algorithm, first, we analyze running time of every function in existing NMS. Then, we calculate execution time and waiting time for these functions. Subsequently, we estimate the transition time between active mode (AM) and low-power mode (LPM). By using these results, we redesign the architecture of NMS in the proposed low-power algorithm: a stimulation signal divided into a number of segments by using characteristics of the signal from which AM or LPM segments are defined for determining the MCU power reduces to turn off or not. Our experimental results indicate that NMS with low-power algorithm reducing current consumption of MCU by 76.31 percent compared to NMS without low-power algorithm.