• Title/Summary/Keyword: low-pass

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A Study on Series Arc Detection Using Band-pass Filters (대역통과필터를 이용한 직렬아크 검출에 관한 연구)

  • Kim, Il-Kwon;Kim, Jin-Su;Park, Keon-Woo;Kim, Kwang-Soon;Kim, Young-Il
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1345-1347
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    • 2008
  • This paper described a method of determining whether arcing is present in a low-voltage wiring system. We simulated the series arcing that generated in electrical loads and fabricated a arc detection module which can discriminate between normal and arcing state. The module consists of a high-pass filter with a low cut-off frequency of 3 kHz to attenuate power frequency voltage and an active band-pass filter with a frequency of 4 kHz ${\sim}$ 8 kHz to detect series arc signals only. We tested an Incandescent lamp that was controlled by a dimmer and analysed. The module consists of a high-pass filter with a low cut-off frequency of 3 kHz to attenuate power frequency voltage by 80 dB and an active band-pass filter with a frequency of 4 kHz to detect series arc signals only. From the experimental results, we could detect series arc signals without an influence of non-linear loads.

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Low-power, fast-locking All Digital Delay Locked-loop Using Complementary Pass-Transistor Logic (상보형 패스 트랜지스터를 이용한 저전력, 고속력 Delay Locked-Loop 설계)

  • 장홍석;정대영;신경민;정강민
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.91-94
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    • 2000
  • This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

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Design of Broadband Hybrid Mixer using Dual-Gate FET (이중게이트 FET 를 이용한 광대역 하이브리드 믹서 설계)

  • Jin, Zhe-Jun;Lee, Kang-Ho;Koo, Kyung-Heon
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.197-200
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    • 2005
  • This paper presents the design of a broadband hybrid mixer using dual-gate FET topology with a low-pass filter which improves return loss of output to isolate RF and LO signal. The low-pass filter shows the isolation whose RF and LO signal is better than 40 dBc at 2 GHz and 5 GHz band. The dual-gate mixer which has been designed by using cascade topology operates when the lower FET is biased in linear region and the upper FET is in saturation. The input matching circuit has been designed to have conversion gain from 2 GHz to 6 GHz. The designed mixer with low-pass filter shows the conversion gain of better than 7 dB from 2 GHz to 6 GHz at a low LO power level of 0 dBm with the fixed IF frequency of 21.4 MHz.

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Implementation of LVRT algorithm of Grid-Connected PCS with Low Pass Notch PLL Technique (LPN(Low Pass Notch) PLL 기법을 활용한 계통연계형 PCS에서의 LVRT 알고리즘 구현)

  • Shin, Dongsul;Lee, Kyoung-Jun;Kim, Hee-Je;Lee, Jong-Pil;Kim, Tae-Jin;Yoo, Dong-Wook
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.516-517
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    • 2014
  • 태양광과 풍력발전 등 분산전원의 대용량 발전이 기존 계통에 미치는 영향이 커짐에 따라, 계통 전압의 안정적인 유지를 위해 필요한 지원이 계통에 연계되는 분산전원들에게 요구되고 있다. 특히나 Low Voltage Ride Through (LVRT) 시에는 계통에서 탈락되지 않는 것은 물론이고, 계통전압 회복을 돕기위해 무효전력을 주입해야 한다. 이러한 사고 상황에서 계통에서 탈락되지 않고 계속적인 계통지원을 위해서는 빠르고 정확한 위상 추종이 필수적이다. 본 논문은 고조파에 강인하고 응답특성이 우수한 Low Pass Notch (LPN) PLL 기법을 LVRT에 적용하여 이의 우수함을 확인한다.

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A Low-power High-resolution Band-pass Sigma-delta ADC for Accelerometer Applications

  • Cao, Tianlin;Han, Yan;Zhang, Shifeng;Cheung, Ray C.C.;Chen, Yaya
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.438-445
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    • 2017
  • This paper presents a low-power high-resolution band-pass ${\Sigma}{\Delta}$ ADC for accelerometer applications. The proposed band-pass ${\Sigma}{\Delta}$ ADC consists of a high-performance 6-th order feed-forward ${\Sigma}{\Delta}$ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of $5mm^2$. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.

Stopband-Extended and Size-Miniaturized Low-Pass Filter with Three Transmission Zeros

  • Li, Lin;Bao, Jia;Du, Jing-Jing;Wang, Yaming
    • ETRI Journal
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    • v.36 no.2
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    • pp.286-292
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    • 2014
  • This paper presents a compact structure composed of an upper high-impedance transmission line, a middle extended parallel coupled line, and a pair of inter-coupled symmetrical stepped impedance stubs. Detailed investigation into this structure based on an equivalent circuit analysis reveals that this proposed structure exhibits a quasi-elliptic low-pass filtering response with three transmission zeros. Moreover, the positions of the three transmission zeros can be tuned and reallocated flexibly by choosing the proper circuit parameters. Finally, the design concept is validated through the design, fabrication, and measurement of two exemplary low-pass filters (LPFs) with one single unit and two cascaded asymmetric units. The measured results agree well with the simulated results. In addition, in the range of $1.42f_c$ to $7.03f_c$, the fabricated quasi-elliptic LPFs experimentally demonstrate a very wide upper-stopband of 20 dB using a compact size of only $0.0089{\lambda}_g{^2}$, where ${\lambda}_g$ is the guided wavelength of a $50{\Omega}$ transmission line at the central frequency.

Low Pass Filter Design using CMOS Floating Resister (CMOS Floating 저항을 이용한 저역통과 필터의 설계)

  • 이영훈
    • Journal of the Korea Society of Computer and Information
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    • v.3 no.2
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    • pp.77-84
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    • 1998
  • The continuous time signal system by development of CMOS technology have been receiving consideration attention. In this paper, Low pass filter using CMOS floating resistor have been designed with cut off frequency for speech signal processing. Especially a new floating resistor consisting entirely of CMOS devices in saturation has been developed. Linearity within $\pm$0.04% is achieved through nonlineartiy via current mirrors over an applied range of $\pm$1V. The frequency response exceeds 10MHz, and the resistors are expected to be useful in implementing integrated circuit active RC filters. The low pass filter designed using this method has simpler structure than switched capacitor filter. So reduce the chip area. The characteristics of the designed low pass filter using this method are simulated by pspice program.

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A Study on the Diplexer Switch of High Isolation Using Varactor Diode (바랙터 다이오드를 이용한 높은 격리도를 갖는 DIPLEXER 스위치에 관한 연구)

  • Kang Myung-Soo;Park Jun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.4
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    • pp.178-184
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    • 2005
  • In this paper, using diplexer structure and varactor diode controlled by reverse bias voltage for diplexer switch gives possibilities to improve isolation and current characteristics. 1 have newly designed switch with high isolation by application varactor diode corresponding to capacitor of diplexer. The low-pass filter for proposed tunable diplexer passes the microwave signal in the bandwidth for wireless cellular network systems and high-pass filter passes it in the bandwidth for wireless personal communication services (PCS) network systems. As the capacitance of the low-pass filter increases, the cut-off frequency can be moved to low frequency, so that the switch is on state in cellular bandwidth and off state in the PCS bandwidth, in contrast to, as the capacitance for attenuation characteristic of high-pass filter increases, it can be moved to high frequency, so that the switch is off state and on state in the cellular bandwidth. it is possible to improve isolation and current consumption characteristics by application diplexer design methods and varactor diode. 1 expect that the tunable diplexer circuit and design methods should be able to find applications on MMIC and low temperature copired ceramic (LTCC).

A Study on DC Offset Removal using Low-Pass Filter in AT Feeder System for Electric Railway (전기철도 AT급전계통에 Low-Pass Filter를 이용한 직류옵셋 제거에 관한 연구)

  • Lee, Hwan;Jung, No-Geon;Kim, Jae-Moon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.6
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    • pp.1108-1114
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    • 2016
  • The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

Performance Analysis on a Low Pass Filter of a CT Saturation Detecting Algorithm Using Difference of the Secondary Current (차분을 이용한 변류기 포화 검출 알고리즘의 저역통과 필터의 영향 분석)

  • Kang, Young-Cheol;Ok, Seung-Hun;Yun, Jae-Sung;Kim, Dae-Sung
    • Proceedings of the KIEE Conference
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    • 2001.07a
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    • pp.249-251
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    • 2001
  • This paper presents performance analysis on a low pass filter of a CT saturation detecting algorithm using difference. At the instants of beginning/end of saturation, the shapes of the secondary current are changed significantly though secondary currents are continuous. At the instants, the second-order or third-order difference of the secondary current has big values because of discontinuity of the first order difference. Thus, the third difference of the current is used to detect the beginning/end of CT saturation. An antialiasing low pass filter removes high frequency components and causes phase lag. A CT saturation detecting algorithm using difference of CT secondary currents is affected by the low pass filter. The algorithm is tested with cutoff frequencies of the filter for the two sampling rates of 64[S/C] and 32 [S/C]. The results of various test cases indicate satisfactory performance of the algorithm.

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