• 인터넷정보학회논문지
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• 제20권5호
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• pp.113-119
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• 2019

최근 상용화된 5G 이동통신의 주요한 특징은 High Data Rate와 Connection Density 그리고 Low Latency로 대표할 수 있는데, 이중 기존 4G와 가장 차별되는 특징은 Low Latency로 다양한 새로운 서비스 제공의 기반이 될 것이다. 이러한 특징을 활용한 서비스로는 AR, 자율주행 등이 검토되고 있으며 관련표준에서도 5G Network Latency 논의를 진행하고 있다. 그러나 서비스 관점의 E2E Latency 논의는 많이 부족한 것이 사실이다. 5G에서 Low Latency를 달성을 위한 최종목표는 RTD 기준 Air Interface 1ms 달성으로 이는 '20년 초 Rel-16을 통한 URLLC(Ultra-reliable Low Latency Communications)를 통해 가능하며, 추가적으로 MEC(Moble Edge Computing)를 통한 Network latency 감소도 연구 중이다. 전체 5G E2E Latency는 5G Network 관련 외에도 다양한 요인이 존재하는데, 주요 요인으로는 5G Network과 서비스 제공을 위한 IDC Server 사이의 경로에 놓인 선로/장비 Latency, 단말 App과 Server 내 서비스 처리를 위한 Processing Latency 등이 존재한다. 한편, 서비스 초기 Setup을 위한 Latency와 서비스가 지속 중인 경우의 Latency를 구분하여 세부 서비스 요구사항에 대하여 연구하는것도 필요한데, 이를 위해 본 논문에서는 서비스 초기 Setup과 관련하여 다음과 같은 세가지 요인에 대하여 검토를 진행하였다. 첫째로 (1) Data호 Setup시에 발생 가능한 Latency, 둘째 전력 효율화를 위한 (2) CRDX On/Off에 따른 영향, 마지막으로 (3) H/O가 발생되는 경우에 Latency에 대하여 Latency에 미치는 영향을 실험과 분석을 제시했다. 이를 통해 우리는 Low Latency가 필요한 서비스의 초기 Setup시에 Latency와 관련된 서비스 요구사항 및 기획에 기여할 수 있을 것으로 기대한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2007년도 추계학술발표대회
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• pp.721-722
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• 2007

MIP(Mobile IP)는 모바일 노드가 서브넷간에 IP 계층의 핸드오프를 가능하게 한다. Low-Latency Handoff 는 이러한 MIP 에서 등록 절차를 조절함으로써 핸드오프 시간을 줄이고 패킷 loss 를 줄이게 한다. 이기종망간 버티컬 핸드오프에서는 보통 Low-Latency Handoff 가 논외로 되어 있으나 모바일 노드가 고속으로 기존망을 벗어날 경우 Low-Latency Handoff 를 적용하면 패킷 loss 를 줄이는 데에 효과를 보게 된다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2013년도 추계학술발표대회
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• pp.259-261
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• 2013

금융 IT와 같은 분야에서는 빅데이터의 큰 특징 중 하나인 Velocity의 개선이 가장 큰 문제이다. 이는 산업의 특성상 승자가 시장을 독식하는 구조로 0.1 초라도 빠른 시스템 속도를 확보하면 시장 경쟁력이 매우 크기 때문이다. 비단 금융 IT 뿐만 아니라 다른 산업들도 최근 보다 빠른 속도의 데이터 처리에 매우 민감하게 반응하는 환경으로 변화하고 있으므로 이에 대한 솔루션이 필요하며 본 연구에서는 폭증스트림의 고속처리를 위한 Low-Latency에 대한 다양한 실험과 환경 구축을 통해 빅데이터의 Velocity 문제를 해결할 수 있는 방안을 제시한다.

• IEIE Transactions on Smart Processing and Computing
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• 제3권1호
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.473-482
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• 2017

Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.

• Journal of Information Processing Systems
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• 제4권4호
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• 한국정보통신학회논문지
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• 제18권11호
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• pp.2658-2663
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• 2014

증권 시스템의 저지연(Low Latency)을 최소화하고 처리 속도 향상을 위해 다양한 기술(Socket Direct Protocol, TCP/IP Offload Engine)이 도입되고 있다. 그러나 고가의 네트워크 장비 지원으로는 속도 개선에 한계가 있으며, 도입 효과 또한 낮은 것이 현실이다. 본 논문에서는 클라우드 환경에서 주식 체결 시스템의 저지연 극복을 위한 SPT(Safe Proper Time) 전송 방식을 제안한다. 이 제안 기법은 커널에 대한 이해를 기반으로 CPU 오버헤드를 줄이기 위해 CPI(Cycle Per Instruction)를 최소화하고, 데이터 전송의 적시성을 만족하는 전송 방식이다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.63-69
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• 2019

Recently, ultra-low latency flash storage devices such as Z-SSD and Optane SSD were introduced with the significant technological improvement in the storage devices which provide much faster response time than today's other NVMe SSDs. With such ultra-low latency, $10{\mu}s$, storage devices the cost of context switch could be an overhead during interrupt-driven I/O completion process. As an interrupt-driven I/O completion process could bring an interrupt handling overhead, polling or hybrid-polling for the I/O completion is known to perform better. In this paper, we analyze tail latency problem in a polling process caused by process scheduling in data center environment where multiple applications run simultaneously under one system and we introduce our adaptive polling selection technique which dynamically selects efficient processing method between two techniques according to the system's conditions.

• International journal of advanced smart convergence
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• 제13권2호
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• pp.7-15
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• 2024

6G network technology represents the next generation of communications, supporting high-speed connectivity, ultra-low latency, and integration with cutting-edge technologies, such as the Internet of Things (IoT), virtual reality, and autonomous vehicles. These advancements promise to drive transformative changes in digital society. However, as technology progresses, the demand for efficient data transmission and energy management between smart devices and network equipment also intensifies. A significant challenge within 6G networks is the optimization of interactions between satellites and smart devices. This study addresses this issue by introducing a new game theory-based technique aimed at minimizing system-wide energy consumption and latency. The proposed technique reduces the processing load on smart devices and optimizes the offloading decision ratio to effectively utilize the resources of Low-Earth Orbit (LEO) satellites. Simulation results demonstrate that the proposed technique achieves a 30% reduction in energy consumption and a 40% improvement in latency compared to existing methods, thereby significantly enhancing performance.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.143-151
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• 2016

This paper presents new prediction methods to improve compression performance of the so-called near-lossless RGB-domain image coder, which is designed to effectively decrease the memory bandwidth of a system-on-chip (SoC) for image processing. First, variable block size (VBS)-based intra prediction is employed to eliminate spatial redundancy for the green (G) component of an input image on a pixel-line basis. Second, inter-color prediction (ICP) using spectral correlation is performed to predict the R and B components from the previously reconstructed G-component image. Experimental results show that the proposed algorithm improves coding efficiency by up to 30% compared with an existing algorithm for natural images, and improves coding efficiency with low computational cost by about 50% for computer graphics (CG) images.