• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.12
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• pp.4912-4933
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• 2015

Information Centric Networking (ICN) has recently attracted great attention. It names the content decoupling from the location and introduces network caching, making the content to be cached anywhere within the network. The benefits of such design are obvious, however, many challenges still need to be solved. Among them, the local caching policy is widely discussed and it can be further divided into two parts, namely the cache permission policy and the cache replacement policy. The former is used to decide whether an incoming content should be cached while the latter is used to evict a cached content if required. The Internet is a user-oriented network and popular contents always have much more requests than unpopular ones. Caching such popular contents closer to the user's location can improve the network performance, and consequently, the local caching policy is required to identify popular contents. However, considering the line speed requirement of ICN routers, the local caching policy whose complexity is larger than O(1) cannot be applied. In terms of the replacement policy, Least Recently Used (LRU) is selected as the default one for ICN because of its low complexity, although its ability to identify the popular content is poor. Hence, the identification of popular contents should be completed by the cache permission policy. In this paper, a cache permission policy called Cache-Filter, whose complexity is O(1), is proposed, aiming to store popular contents closer to users. Cache-Filter takes the content popularity into account and achieves the goal through the collaboration of on-path nodes. Extensive simulations are conducted to evaluate the performance of Cache-Filter. Leave Copy Down (LCD), Move Copy Down (MCD), Betw, ProbCache, ProbCache⁺, Prob(p) and Probabilistic Caching with Secondary List (PCSL) are also implemented for comparison. The results show that Cache-Filter performs well. For example, in terms of the distance to access to contents, compared with Leave Copy Everywhere (LCE) used by Named Data Networking (NDN) as the permission policy, Cache-Filter saves over 17% number of hops.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.27-34
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• 2012

In this paper, the implementation of high throughput two-dimensional (2-D) $8{\times}8$ forward and inverse integer DCT transform for H.264 is presented. The forward and inverse transforms are represented using simple shift and addition operations. Matrix decomposition and matrix operation such as the Kronecker product and direct sum are used to reduce the computation complexity. The proposed design uses integer computations and does not use transpose memory and hence, the resource consumption is also reduced. The maximum operating frequency of the proposed pipelined architecture is 1.184 GHz, which achieves 25.27 Gpixels/sec throughput rate with the hardware cost of 44864 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of Institute of Control, Robotics and Systems
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• v.2 no.4
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• pp.306-311
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• 1996

This paper discusses the maintenance of the water level of steam generators at its programmed value. The process, the water level of a steam generator, has the nonminimum phase property. So, it causes a reverse dynamics called a swell and shrink phenomenon. This phenomenon is severe in a low power condition below 15 %, in turn makes the start-up of the power plant too difficult. The control algorithm used here incorporates a pole-assignment scheme into the minimum variance strategy and we use a parallel adaptation algorithm for the parameter estimation, which is robust to noises. As a result, the total control system can keep the water level constant during full power by locating closed-loop poles appropriately, although the process has the characteristics of high complexity and nonlinearity. Also, the extra perturbation signals are added to the input signal such that the control system guarantee persistently exciting. In order to confirm the control performance of a proposed pole-assignment self-tuning controller we perform a computer simulation in full power range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1534-1540
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• 2005

The direct conversion method is classified into the structure using the mixing technology and six-port scheme. In the view point of complexity and integration the direct conversion method using the six-port scheme is superior to that with mixing technology. Expecially, the six-port direct conversion technology provides the low power consumption and the broad-band characteristic. In this paper, the six-port direct conversion receiver with the branch-line coupler and the ring hybrid coupler is desisted respectively. The performances of the designed six-port schemes are analyzed and the six-port scheme with superior performance characteristics is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.14-19
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• 2006

The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this parer, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11B
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• pp.1169-1177
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• 2009

This paper presents an energy efficient MAC protocol for delay-sensitive data transmission over wireless sensor network. In general, energy consumption and delay depend on Channel Monitoring Interval and data sensing period at each sensor node. Based on this fact, we propose a new preamble structure to effectively advertise Channel Monitoring Interval and avoid the overhearing problem. In order to pursue an effective tradeoff between energy consumption and delay, we also develop a Channel Monitoring Interval determining algorithm that searches for a sub-optimal solution with a low computational complexity. Finally, experimental results are provided to compare the proposed MAC protocol with existing sensor MAC protocols.

• Journal of Communications and Networks
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• v.16 no.5
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• pp.568-577
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• 2014

We consider a mobile content delivery network (mCDN) in which special mobile devices designated as caching servers (caching-server device: CSD) can provide mobile stations with popular contents on demand via device-to-device (D2D) communication links. On the assumption that mobile CSD's are randomly distributed by a Poisson point process (PPP), an optimization problem is formulated to determine the probability of storing the individual content in each server in a manner that minimizes the average caching failure rate. Further, we present a low-complexity search algorithm, optimum dual-solution searching algorithm (ODSA), for solving this optimization problem. We demonstrate that the proposed ODSA takes fewer iterations, on the order of O(log N) searches, for caching N contents in the system to find the optimal solution, as compared to the number of iterations in the conventional subgradient method, with an acceptable accuracy in practice. Furthermore, we identify the important characteristics of the optimal caching policies in the mobile environment that would serve as a useful aid in designing the mCDN.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.