• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.97-102
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• 2007

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is implementation of a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.7-12
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• 2005

Scattered look-ahead(SLA) pipelining method can be efficiently used for high-speed or low-power applications of digital II R filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large roundoff noise when the poles are crowded within some critical regions. An angle and radius constrained II R fille. design approach using modified Remez exchange algorithm and least squares algorithm is proposed to avoid tight pole-crowding in pipelined filters, resulting in improved frequency responses and reduced coefficient sensitivities. Experimental results demonstrate that our proposed method leads to chip area reduction by $33{\%}$ and low power by $45{\%}$ against the conventional method.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1280-1283
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• 2002

This paper discusses issues in VLSI design and implementation of high performance datapath circuits. Of particular concern will he various types of multiplier and adder, which are fundamental to DSP operations. Performance comparison will be provided in terms of sampling speed, layout area, and in particular, power consumption, with techniques that may be applied to reduce power dissipation also suggested. As an example, a low power, high performance recursive filter achieved through bit-level pipelining technique is illustrated

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.232-235
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• 1999

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

• Korean Institute of Interior Design Journal
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• v.16 no.5
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• pp.55-62
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• 2007

Modern public library is expanding its role as generalized cultural facility. Therefore public library that has comfortable and physical environment for various age and various users are needed. The purpose of this research is to evaluate the application of universal design in common space of public library, and trying to suggest environmental improvement plan that various users could comfortably use the library based on its data. The scope of this research were adjusted as 8 public libraries located in Seoul and metropolitan area of Seoul. Spacial scope that was set of this research was common space of public library and scope of content was about application of universal design. As a result of the research, first, the application of universal design toward common space of public library were appeared as low. Second, constant management and application development of universal design is needed. Third, as roles and functions of public library become various from now on, application of delicate universal design is needed for intention of users.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.35-41
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• 2012

Due to the technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft error because of the highly integrated transistors, and consequently, the reliability of the cache memory must consider seriously at the design space level. In this paper, we propose the reliability improving technique which can be achieved with low energy and low area overheads. The simulation experiments of the proposed scheme shows over 95.4% of protection rate against the soft error with only 0.26% of performance degradations. Also, It requires only 2.96% of extra energy consumption.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.2
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• pp.87-94
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• 2007

It has been argued that the use of plastics can cause problems during design and manufacture owing to their low strength, relatively poor thermal conductivity and large thermal expansion. However, the advantages of plastics e.g., corrosion resistance, low cost, curtailment of weight, design flexibility etc., can compensate abundantly for the disadvantages. This study analyzes and compares the heat transfer performance characteristics of automotive compact oil cooler composed of plastic tube bundle with conventional metal oil cooler on the same core area basis as diameter, tube thickness, number of tube or tube arrangement varies. The performance analyses are accomplished by use of computational fluid dynamics program Fluent 6.2, which is verified and compared with the results of performance tests. The result of analyses is coincided with that of experiments. Flow pattern at air side according to tube arrangement is dominant factor which affects heat dissipation in case of similar total heat transfer surface area.

• Journal of the Korean Solar Energy Society
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• v.29 no.6
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• pp.62-68
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• 2009

There has been a continuous increase in the utilization and utility value of renewable energy such as wind power generation in modem society. Wind condition is the absolute variable to the energy volume in the case of a wind power generation system. For this reason, wind power generators have already been installed in areas where wind velocity is high and the possibility of danger is very low. In other words, instability is likely if the wind velocity in an area is high and where a wind power generation system can be built. On the contrary, low wind velocity is possible in an area with high stability. Therefore, the design and manufacture of a wind power generation system should be carried out in a more complicated topography in order to secure a bigger market. This study examines and suggest how topography affects wind shear by analyzing the measured data in order to predict wind power generation more reliably.