• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.4
• /
• pp.94-101
• /
• 2009

In this paper, we propose design of hardware based on a high speed digital signal processor (DSP) and a field programmable gate array (FPGA) for real-time suppression of fixed pattern noise (FPN) using hardware neural networks (HNN) in cooled infrared focal plane array (IRFPA) imaging system FPN appears a limited operation by temperature in observable images which applies to non-uniformity correction for infrared detector. These have very important problems because it happen serious problem for other applications as well as degradation for image quality in our system Signal processing architecture for our system operates reference gain and offset values using three tables for low, normal, and high temperatures. Proposed method creates virtual tables to separate for overlapping region in three offset tables. We also choose an optimum tenn of temperature which controls weighted values of HNN using mean values of pixels in three regions. This operates gain and offset tables for low, normal, and high temperatures from mean values of pixels and it recursively don't have to do an offset compensation in operation of our system Based on experimental results, proposed method showed improved quality of image which suppressed FPN by change of temperature distribution from an observational image in real-time system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.8
• /
• pp.1759-1764
• /
• 2012

This paper describes FPGA design and realization using the shading correction algorithm for a CCD scan image enhancement. The shading algorithm is used by LUT (Look-up Table). The image enhancement results from that the histogram minimum value and maximum with respect to all pixels of the CCD image should be extracted, and the shading LUT is constructed to keep constant histogram with offset data. The output of sensor be converted to corrected LUT image in preprocessing, and the converting system is realized by FPGA to be enabled to operate in real time. The result of the experimentation for the proposed system is showed to take the scanning time 2.4ms below. The system is presented to be based on a low speed processor system to scan enhanced images in real time and be guaranteed to be low cost.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.5
• /
• pp.97-105
• /
• 2017

An air-burst munition is limited in space, so there is a limit on the size of the fuze and the amount of ammunition. In order to increase a firepower to a target with limited ammunition, it is necessary to concentrate the firepower on the ground instead of the omnidirectional explosion after flying to the target. This paper explores the design and verification of a ground-detection sensor that detects the direction of the ground and determines the flight-distance of an air-burst munition using a single axis geomagnetic sensor. Prior to the design of the ground detection sensor, a geomagnetic sensor model mounted on the spinning air-burst munition is analyzed and a ground-detection algorithm by simplifying this model is designed. A high speed rotating device to simulate a rotation environment is designed and a geomagnetic sensor and a remote-recording system are fabricated to obtain geomagnetic data. The ground detection algorithm is verified by post-processing the acquired geomagnetic data. Taking miniaturization and low-power into consideration, the ground detection sensor is implemented with analog devices and the processor. The output signal of the ground detection sensor rotating at an arbitrary rotation speed of 200 Hz is connected to the LED (Light Emitting Diode) in the high speed rotating device and the ground detection sensor is verified using a high-speed camera.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.9 s.351
• /
• pp.53-58
• /
• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• 한국ITS학회:학술대회논문집
• /
• v.2007 no.10
• /
• pp.225-229
• /
• 2007

Recently, wireless sensor networks are deployed in various applications range from simple environment monitoring systems to complex systems, which generate large amount of information, like motion monitoring, military, and telematics systems. Although wireless sensor network nodes are operated with low-power 8bit processor to execute simple tasks like environment monitoring, the nodes in these complex systems have to execute more difficult tasks. Generally, MAC protocols for wireless sensor networks attempt to reduce the energy consumption using duty cycling mechanism which means the nodes periodically sleep and wake. However, in the duty cycling mechanism. a node should wait until the target node wakes and the sleep latency increases as the number of hops increases. This sleep latency can be serious problem in complex and sensitive systems which require high speed data transfer like military, wing of airplane, and telematics. In this paper, we propose a solution for reducing transmission latency through distributed duty cycling (DDC) in wireless sensor networks. The proposed algorithm is evaluated with real-deployment experiments using CC2420DBK and the experiment results show that the DDC algorithm reduces the transmission latency significantly and reduces also the energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.24-30
• /
• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of Korean Society for Geospatial Information Science
• /
• v.19 no.3
• /
• pp.41-47
• /
• 2011

Processing of the raw LiDAR data requires the high-end processor, because data form is a vector. In contrast, if LiDAR data is converted into a regular grid pattern by filltering, that has advantage of being in a low-cost equipment, because of the simple structure and faster processing speed. Especially, by using grid data classification, such as Quadtree, some of trees and cars are removed, so it has advantage of modeling. Therefore, this study presents the algorithm for automatic extraction of ground points using Quadtree and refion growing method from LiDAR data. In addition, Error analysis was performed based on the 1:5000 digital map of sample area to analyze the classification of ground points. In a result, the ground classification accuracy is over 98%. So it has the advantage of extracting the ground points. In addition, non-ground points, such as cars and tree, are effectively removed as using Quadtree and region growing method.

• The KIPS Transactions:PartA
• /
• v.10A no.4
• /
• pp.397-404
• /
• 2003

Dedicated-purpose embedded Java system usually takes such model that all class files are converted into a single ROM Image by the ROMizer in the host computer, and then the Java virtual machine in the embedded system executes the image. Defining the ROM Image is a very important issue for embedded system with limited memory resource and low-performance processor since the format directly influences on the memory usage and effectiveness of accessing entries in classes. In this paper we have analyzed the ROMizer and especially the format of the ROM image implemented in the simpleRTJ embedded Jana virtual machine. The analysis says that memory space can be saved up to 50% compared to the original class file and access speed exceeds up to six times with the use of the ROMizer. The result of this study will be applied to develop a more efficient ROMizer for a ROM-based embedded Java system.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.3
• /
• pp.381-387
• /
• 2011

Measurement controller that acquire and control and observe data from scattering sensors is organic with central control room. Therefore, measurement controller is efficient wireless network than wire network. But, serious problem is happened in security from outside if use wireless network. Therefore, this paper proposed suitable MS-WP cryptographic system to measurement control wireless network to augment network efficiency of measure controller. Result that implement proposed MS-WP cryptographic system by chip level and achieve a simulation, confirmed that 130% processing rate increase and system efficiency are increased double than AES algorithm. Proposed MS-WP cryptographic system augments security and is considered is suitable to measurement controller because that low power is possible and the processing speed is fast.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.12
• /
• pp.11-19
• /
• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.