• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.248-253
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• 2005

We designed and fabricated a compact multi-mode interference (MMI) wavelength demultiplexer using the concept of 'Improved Quasi-State' modes. The output power and extinction ratio were improved by utilizing modal phase error which is specially occurred in low-index contrast. For a designed demultiplexer, the mode propagation analysis with effective index approximation shows significant improvement of extinction ratio to -25 dB for both $1.31{\mu}m\;and\;1.51{\mu}m$ wavelength region and the split-length was reduced about 1/5 of other MMI devices. The fabricated device shows successful characteristics for both 1.31 and $1.55{\mu}m$ wavelengths. These results demonstrate the potential of low-index materials system and the embossing process for photonic integrated circuits.

• Journal of Adhesion and Interface
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• v.2 no.2
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• pp.1-10
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• 2001

Silica for Epoxy Molding Compound (EMC) was coated via plasma-polymerization with RF plasma (13.56 MHz) as a function of treatment time, power and pressure. 1,3-diaminopropane, allylamine, pyrrole, 1,2-epoxy-5-hexene, allylmercaptan or allylalcohol were utilized for plasma polymerization coating and adhesion of coated silica was evaluated by measuring flexural strength. CTE and water absorption of EMC were also measured, and fracture surface of flexural specimen was analyzed by SEM in order to elucidate the failure mode. The plasma polymer coated silica was analyzed by FT-IR and reactivity of plasma polymer coating with epoxy resin was evaluated with DSC in order to investigate the adhesion mechanism. The EMC prepared from the silica coated with 1,3-diaminopropane or allylamine exhibited high flexural strength, low CTE, and low water absorption compared with the control sample, and also exhibited 100% cohesive failure mode. These results can be attributed to the chemical reaction between the functional groups in the plasma polymer coating and epoxy resin, and also consistent with the results from FT-IR and DSC analysis.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• International Journal of Fluid Machinery and Systems
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• v.10 no.1
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• pp.40-46
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• 2017

Small valves including ball valves, gate valves and butterfly valves have been adopted in the fields of steam power generation, petrochemical industry, carriers, and oil tankers. Butterfly valves have normally been applied to fields where in narrow places installing the existing valves such as gate valves and ball valves have proven difficult due to the surrounding area and the heavier of these valves. Butterfly valves are used to control the mass flow of the piping system under low pressure by rotating the circular disk installed inside. The butterfly valve is benefitted by having simpler structure in which the flow is controlled by rotating the disc circular plate along the center axis, whereas the weight of the valve is light compared to the gate valve and ball valve above-mentioned, as there is no additional bracket supporting the valve body. The manufacturing company needs to acquire the performance and life test equipment, in the case of adopting the improving factors to detect leakage and damage on the seat of the valve disc. However, small companies, which are manufacturing the industrial valves, normally sell their products without the life test, which is the reliability test and environment test, because of financial and manpower problems. Furthermore, the failure mode analysis of the products failed in the field is likewise problematic as there is no system collecting the failure data on sites for analyzing the failures of valves. The analyzing and researching process is not arranged systematically because of the financial problem. Therefore this study firstly tried to obtain information about the failure data from the sites, analyzed the failure mode based on the field data collected from the customers, and then obtained field data using measuring equipment. Secondly, we designed and manufactured the performance and life test equipment which also have the real time monitoring system with the naked eye for the butterfly valves. The concept of this equipment can also be adopted by other valves, such as the ball valve, gate valve, and various others. It can be applied to variously sized valves, ranging from 25 mm to large sized valves exceeding 3000 mm. Finally, this study carries out the life test with square wave pressure, using performance and life test equipment. The performance found out that the failures from the real time monitoring system were good. The results of this study can be expanded to the other valves like ball valves, gate valves, and control valves to find out the failure mode using the real time monitoring system for durability and performance tests.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4177-4185
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• 2012

LEDs are becoming the most suitable candidate replacing traditional fluorescent lamps because of its eco-friendly characteristics. LEDs are also actively used to design green building system and to make outdoor billboard as a back-light system due to its high energy efficiency. In this paper, we have developed AC direct driver for $12{\times}12$ FLB(flexible LED board) and LED flat light without SMPS. It has LID-PC-R101B driver IC that can support the high power factor and be composed of LED switching circuit in group. Also, an elaborate system designs can guarantee a high luminous efficiency, a high reliability and a low power consumption. The proposed FLB has the ultra slim shape of $450{\times}450$ mm, width of 4 mm and weight of 280 g. In the end, we have developed a prototype of FLB for billboard and flat light for room lighting with AC direct driver iposrder to verify the performance of the proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1050-1060
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• 2009

In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than $4^{\circ}$ max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.