• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.299-304
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• 2008

For perpendicular magnetic recording channels, it is hard to expect improving the performance by using the PRML or NPML. Hence, we exploit LDPC code to improve the performance. In this paper, we examine a single message-passing detector/decoder matched to the combination of a perpendicular magnetic recording channel detector and an LDPC code decoder. We examine the performance of channel iteration with joint LDPC code on perpendicular magnetic recording channel, and simplify the complexity of the message-passing detector algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.132-132
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• 2004

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.463-471
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• 2019

This paper proposes a method for reducing the complexity of LIC (Local Illuminance Compensation) for bi-directional inter prediction. The LIC performs local illumination compensation using neighboring reconstruction samples of the current block and the reference block to improve the accuracy of the inter prediction. Since the weight and offset required for local illumination compensation are calculated at both sides of the encoder and decoder using the reconstructed samples, there is an advantage that the coding efficiency is improved without signaling any information. Since the weight and the offset are obtained in the encoding prediction step and the decoding step, encoder and decoder complexity are increased. This paper proposes two methods for low complexity LIC. The first method is a method of applying illumination compensation with offset only in bi-directional prediction, and the second is a method of applying LIC after weighted average step of reference block obtained by bidirectional prediction. To evaluate the performance of the proposed method, BD-rate is compared with BMS-2.0.1 using B, C, and D classes of MPEG standard experimental image under RA (Random Access) condition. Experimental results show that the proposed method reduces the average of 0.29%, 0.23%, 0.04% for Y, U, and V in terms of BD-rate performance compared to BMS-2.0.1 and encoding/decoding time is almost same. Although the BD-rate was lost, the calculation complexity of the LIC was greatly reduced as the multiplication operation was removed and the addition operation was halved in the LIC parameter derivation process.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1143-1149
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• 2006

In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.37-42
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• 2019

In this paper, we propose a syndrome decoding scheme that can correct two errors for single error correcting Hamming codes within a code length. The decoding scheme proposed in this paper has the advantage of significantly improving the error rate performance compared to the decoder complexity by correcting multiple errors without substantially increasing the decoding complexity. It is suitable for applications in which the energy use of encoder/decoder is extremely limited and the low error rate performance is required, such as IoT communications and molecular communications. In order to verify the improvement of the error rate performance of the Hamming code with the proposed decoding scheme, we performed simulation on Hamming codes with short code length in the AWGN and BPSK modulation environments. As a result, compared with the conventional decoding method, the proposed decoding scheme showed performance improvement of about 1.1 ~ 1.2[dB] regardless of the code length of the Hamming code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.391-399
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• 2006

We propose a novel low complexity video encoder, at the expense of a complex decoder, where video frames are intra-coded periodically and frames in between successive intra-coded frames are coded efficiently using a proposed irregular binning technique. We investigate a method of forming an irregular binning which is capable of quantizing any value effectively with only small number of bins, by exploiting the correlation between successive frames. This correlation is additionally exploited at the decoder, where the quality of reconstructed frames is enhanced gradually by applying POCS(projection on the convex sets). After an image frame is reconstructed with the irregular binning information at the proposed decoder, we can further improve the resulting quality by modifying the reconstructed image with motion-compensated image components from the neighboring frames which are considered to contain image details. In the proposed decoder, several iterations of these modification and re-projection steps can be invoked. Experimental results show that the performance of the proposed coding scheme is comparable to that of H.264/AVC coding in m mode. Since the proposed video coding does not require motion estimation at the encoder, it can be considered as an alternative for some versions of H.264/AVC in applications requiring a simple encoder.