• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.1-13
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• 2011

In this paper, we propose an adaptive in-loop filter to improve the coding efficiency. Recently, there are post-filter hint SEI and block-based adaptive filter control (BAFC) methods based on the Wiener filter which can minimize the mean square error between the input image and the decoded image in video coding standards. However, since the post-filter hint SEI is applied only to the output image, it cannot reduce the prediction errors of the subsequent frames. Because BAFC is also conducted with a deblocking filter, independently, it has a problem of high computational complexity on the encoder and decoder sides. In this paper, we propose the low-complexity adaptive in-loop filter (LCALF) which has lower computational complexity by using H.264/AVC deblocking filter, adaptively, as well as shows better performance than the conventional method. In the experimental results, the computational complexity of the proposed method is reduced about 22% than the conventional method. Furthermore, the coding efficiency of the proposed method is about 1% better than the BAFC.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.6
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• pp.665-674
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• 2001

In this paper, a reduced complexity fillet to simultaneously suppress the blocking and ringing artifacts of compressed video sequence is addressed. A new one dimensional regularized function to incorporate the smoothness to its neighboring pixels into the solution is defined, resulting in very low complexity filter The proposed regularization function consists of two sub-functions that combine local data fidelity and local smoothing constraints. The regularization parameters to control the trade-off between the local fidelity to the data and the smoothness are determined by available overhead information in decoder, such as maroc-block type and quantization step size. In addition, the regularization parameters are designed to have the limited range and stored as look-up-table, and therefore, the computational cost to determine the parameters can be reduced. The experimental results show the capability and efficiency of the proposed algorithm.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.95-100
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• 2002

By feedback channel, the decoder reports the addresses of corrupted macroblocks induced by transmission errors back to the encoder With these negative acknowledgements, the encoder can make the next frame having propagated errors by using forward dependency based on GOBs and MBs of the frame happening transmission errors. The encoder can precisely calculate and track the propagated errors by examining the backward motion dependency for each of four comer pixels in the current encoding frame until before-mentioned the next frame. The error-propagation effects can be terminated completely by INTRA refreshing the affected macroblocks. Such a fast algorithm further reduce the computation and memory requirements. The advantages of the low computation complexity and the low memory requirement are Particularly suitable for real-time implementation.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.3
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• pp.142-152
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• 2014

Vehicular Ad-hoc Networks (VANETs) are comprised of wireless mobile nodes characterized by a randomly changing topology, high mobility, availability of geographic position, and fewer power constraints. Orthogonal Frequency Division Multiplexing (OFDM) is a promising candidate for the physical layer of VANET because of the inherent characteristics of the spectral efficiency and robustness to channel impairments. The susceptibility of OFDM to Inter-Carrier Interference (ICI) is a challenging issue. The high mobility of nodes in VANET causes higher Doppler shifts, which results in ICI in the OFDM system. In this paper, a frequency domain com-btype channel estimation was used to cancel out ICI. The channel frequency response at the pilot tones was estimated using a Least Square (LS) estimator. An efficient interpolation technique is required to estimate the channel at the data tones with low interpolation error. This paper proposes a robust interpolation technique to estimate the channel frequency response at the data subcarriers. The channel induced noise tended to degrade the Bit Error Rate (BER) performance of the system. Parallel concatenated Convolutional codes were used for error correction. At the decoding end, different decoding algorithms were considered for the component decoders of the iterative Turbo decoder. A performance and complexity comparison among the various decoding algorithms was also carried out.

• Journal of Korea Multimedia Society
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• v.20 no.5
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• pp.731-739
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• 2017

Distributed compressed video sensing (DCVS) is a framework that integrates both compressed sensing and distributed video coding characteristics to achieve a low complexity video sampling. In DCVS schemes, motion estimation & motion compensation is employed at the decoder side, similarly to distributed video coding (DVC), for a low-complex encoder. However, since a simple BCS-SPL algorithm is applied to a residual arising from motion estimation and compensation in conventional MC-BCS-SPL (motion compensated block compressed sensing with smoothed projected Landweber) scheme, the reconstructed visual qualities are severly degraded in Wyner-Ziv (WZ) frames. Furthermore, the scheme takes lots of iteration to reconstruct WZ frames. In this paper, the conventional MC-BCS-SPL algorithm is improved to be operated in more effective way in WZ frames. That is, first, the proposed algorithm calculates a correlation coefficient between two reference key frames and, then, by selecting adaptively the reference frame, the residual reconstruction in pixel domain is performed to the conventional BCS-SPL scheme. Experimental results show that the proposed algorithm achieves significantly better visual qualities than conventional MC-BCS-SPL algorithm, while resulting in the significant reduction of the decoding time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.450-458
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• 2008

In this paper, we propose a real-time stereoscopic display system based on H.264/AVC. We initially acquire stereo-view images from stereo web-cam using OpenCV library. The captured images are converted to YUV 4:2:0 format as a preprocess. The input files are encoded by stereo-encoder, which has a proposed estimation structure, with more than 30 fps. The encoded bitstream are decoded by stereo-decoder reconstructing left and right images. The reconstructed stereo images are postprocessed by stereoscopic image synthesis technique to offer users more realistic images with 3D effect. Experimental results show that the proposed system has better encoding efficiency compared with using a conventional stereo CODEC(coder and decoder) and operates with real-time processing and low complexity suitable for an application with a mobile environment.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.513-526
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• 2010

In this paper, we propose a de-blocking filter for improvement of coding efficiency and computational complexity reduction on a high definition video coding. Recently, the H.264/AVC standard-based research for high definition video coding method is under way because the amount of used of high definition videos is on the increase. The H.264/AVC de-blocking filter is designed for low bitrate video coding and it improves not only the subjective quality but also coding efficiency by minimizing the blocking artifact. However, the H.264/AVC de-blocking filter that strong filtering is performed is not suitable in a high definition video coding which occurs relatively low blocking artifact. Also, the conventional de-blocking filter has high computational complexity in decoder side. The computational complexity of the proposed method is reduced about maximum 8.8% than conventional method. Furthermore, the coding efficiency of the proposed method is about maximum 7.3% better than H.264/AVC de-blocking filter.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Proceedings of the Korea Contents Association Conference
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• 2003.11a
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• pp.328-332
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• 2003

Since Jacquine introduced the image coding algorithm using fractal theory, many fractal image compression algorithms providing good quality at low bit rate have been proposed by Fisher and Beaumount et al.. But a problem of the previous implementations is that the decoding rests on an iterative procedure whose complexity is image -dependent. This paper proposes an iterative-free fractal image decoding algorithm to reduce the decoding time. In the proposed method, under the encoder previously with the same codebook image as an initial image to be used at the decoder, the fractal coefficients are obtained through calculating the similarity between the codebook image and a input image to be encoded. As the decoding process can be completed with received fractal coefficients and predefined initial image without repeated iterations, the decoding time could be remarkably reduced.