• The Journal of Korea Robotics Society
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• v.13 no.2
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• pp.129-141
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• 2018

This paper proposes a unified framework that overcomes four motion constraints including joint limit, kinematic singularity, algorithmic singularity and obstacles. The proposed framework is based on our previous works which can insert or remove tasks continuously using activation parameters and be applied to avoid joint limit and singularity. Additionally, we develop a method for avoiding obstacles and combine it into the framework to consider four motion constraints simultaneously. The performance of the proposed framework was demonstrated by simulation tests with considering four motion constraints. Results of the simulations verified the framework's effectiveness near joint limit, kinematic singularity, algorithmic singularity and obstacles. We also analyzed sensitivity of our algorithm near singularity when using closed loop inverse kinematics depending on magnitude of gain matrix.

• Transactions of the Society of Information Storage Systems
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• v.3 no.1
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• pp.5-12
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• 2007

This paper investigates the design of disturbance observer for rotational vibration suppression in disk drive systems. The design aims to provide an optimal controller which satisfies both vibration performance and robust stability. It consists of an inversion method, a special filter, and optimization scheme. Firstly a new inversion method is introduced, which provides more accurate inversion compared to conventional zero phase error method. The inversion is to deal with unstable zeros in the plant model. Secondly a special filter for disturbance selection is given, which features adjustable gain and band pass characteristics so that it enables flexible shaping of the loop considering the trade-off between performance and stability margins. And finally the parameters of disturbance observer are optimized in conjunction with external disturbance model. Simulation and experiment on commercial hard disk drives confirm that the design is very effective to such disturbance which is hard to be handled by conventional approach.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• International Journal of Control, Automation, and Systems
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• v.2 no.3
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• pp.374-383
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• 2004

This paper presents a neural network adaptive controller for autonomous diving control of an autonomous underwater vehicle (AUV) using adaptive backstepping method. In general, the dynamics of underwater robotics vehicles (URVs) are highly nonlinear and the hydrodynamic coefficients of vehicles are difficult to be accurately determined a priori because of variations of these coefficients with different operating conditions. In this paper, the smooth unknown dynamics of a vehicle is approximated by a neural network, and the remaining unstructured uncertainties, such as disturbances and unmodeled dynamics, are assumed to be unbounded, although they still satisfy certain growth conditions characterized by 'bounding functions' composed of known functions multiplied by unknown constants. Under certain relaxed assumptions pertaining to the control gain functions, the proposed control scheme can guarantee that all the signals in the closed-loop system satisfy to be uniformly ultimately bounded (UUB). Simulation studies are included to illustrate the effectiveness of the proposed control scheme, and some practical features of the control laws are also discussed.

• Journal of Power Electronics
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• v.3 no.3
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• pp.185-196
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• 2003

In this paper, the single-phase static VAR compensator (SVC) is applied to regulate and stabilize the generated terminal voltage of the single-phase self-excited induction generator (single-phase SEIG) driven by a variable-speed prime mover (VSPM) under the conditions of the independent inductive load variations and the prime mover speed changes The conventional fixed gain PI controller-based feedback control scheme is employed to adjust the equivalent capacitance of the single-phase SVC composed of the fixed excitation capacitor FC in parallel with the thyristor switched capacitor TSC and the thyristor controlled reactor TCR The feedback closed-loop terminal voltage responses in the single-phase SEIG coupled by a VSPM with different inductive passive load disturbances using the single-phase SVC with the PI controller are considered and discussed herem. A VSPM coupled the single-phase SEIG prototype setup is established. Its experimental results are illustrated as compared with its simulation ones and give good agreements with the digital simulation results for the single-phase SEIG driven by a VSPM, which is based on the SVC voltage regulation feedback control scheme.

• Journal of Power Electronics
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• v.16 no.3
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• pp.849-860
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• 2016

The high-switching-frequency operation of power converters can achieve high power density through size reduction of passive components, such as capacitors, inductors, and transformers. However, a small-output capacitor that has small capacitance and low effective series resistance changes the small-signal model of the converter power stage. Such a capacitor can make the converter unstable by increasing the crossover frequency in the transfer function of the small-signal model. In this paper, the design and implementation of a high-frequency LLC resonant converter are presented to verify the power density enhancement achieved by decreasing the size of passive components. The effect of small output capacitance is analyzed for stability by using a proper small-signal model of the LLC resonant converter. Finally, proper design methods of a feedback compensator are proposed to obtain a sufficient phase margin in the Bode plot of the loop gain of the converter for stable operation at 500 kHz switching frequency. A theoretical approach using MATLAB, a simulation approach using PSIM, and experimental results are presented to show the validity of the proposed analysis and design methods with 100 and 500 kHz prototype converters.

• Proceedings of the KIEE Conference
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• 1998.07c
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• pp.1195-1199
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• 1998

In this paper a design method of robust power system stabilizers is proposed by means of robust linear quadratic regulator design technique under power system's operating condition change, which is caused by inner structure uncertainties and disturbances into a power system. It is assumed that the uncertainties present in the system are modeled as one equivalent signal. In this connections an optimal LQR control input for disturbance rejection, the output feedback gain for eliminating the disturbance are calculated. In this case. PSS input signal is obtained on the basis of weighted ${\Delta}P_e$ and $\Delta\omega$. In order to stabilize the overall control of system. Pole placement algorithm is applied in addition. making the poles of the closed loop system to move into a stable region in the complex plane. Some simulations have been conducted to verify the feasibility of the proposed control method on a machine to infinite bus power system. From the simulation results validation of the proposed method could be achieved by comparisons with the conventional PSS with phase lag-lead compensation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.5
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• pp.8-15
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• 2011

LTE-Advanced aims at peak data rates of 1Gbits/s for the downlink and 500 Mbits/s for the uplink, which can be accomplished only by using wide spectrum allocation of 100MHz as well as advanced multiple input multiple output antenna techniques to the uplink. This paper analyzes the uplink precoding techniques which include LTE codebook of downlink, singular value decomposition codebook, and equal gain transmission codebook over LTE defined single carrier frequency division multiplexing systems. Finally considering nonlinear transmit power amplifier model, it is shown that link-level performance of EGT is superior to those of any other precoding schemes.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.4
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• pp.347-355
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• 2005

In this paper, a new continuous~time small signal model of an average current mode control is proposed. Sampling effect Is considered to obtain the proposed small signal model. By the proposed model, the high frequency response characteristics of current loop gain might be predicted accurately compared to previous models. And this leads the prediction of inductor current response of the proposed model to be accurate compared to others. In order to show the usefulness of the proposed model, prediction results of the proposed model are compared to those of the circuit level simulator, PSIM and experiment.