• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.1025-1026
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• 2011

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.39.4-39
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• 2002

This paper presents a design and implementation of a PID feedback control loop for micro gyroscope. The feedback control loop improves the gyroscope performance such as linearity, bandwidth, and bias stability for micro gyroscope which is basically a high-Q system and exhibits a low performance with an open loop control. The designed and implemented feed-back control loop is applied to the SNU-Bosch MEMS gyroscope to demonstrate the improvement with the feedback control loop. The bandwidth is improved to 60Hz from 25Hz of open loop control. The linearity becomes 0.5% from 1%. The bias stability is improved to 0.03 deg/sec from 0.06 deg/sec.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.357-358
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• 2018

The track radar use the range track loop to track the target range. The bandwidth of the radar range tracker can be determined by tradeoff according to signal to noise ratio and the target range. On the other hand, electronic warfare is carried out to prevent the radar from tracking targets by electronic attack. The deception or noise jamming in electronic warfare can be performed to interfere with the range track loop of the radar. In order to efficiently perform electronic warfare, the bandwidth in radar tracking loop is estimated and can be used for electronic attack. To do this, we have studied the method of estimating the bandwidth of radar tracking loop using the variables that can be gathered in electronic warfare.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.12 no.3
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• pp.17-24
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• 2003

One of the most important performance criteria related to the gain tuning of controller for CNC machining center is the contour error. This study analyzed circular error by the axis-matched and mismatched cases. To reduce ellipse and radius error, it is necessary to set the gain for each axis to be same bandwidth and high response. Based on the analysis in the frequency domain, we simulate feed system by mathematical model and then predict bandwidth of each axis. For analysis of structure vibration while the each axis is moving, we try the various of measuring method and position loop is improved by jerk limit.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.39.3-39
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• 2002

In this paper, presented is a feedback control loop, for an in-plane gimbaled micro gyroscope based on methodology and state weighted model reduction technique. The micro gyroscope is the basic inertial sensors. To improve the performances such as stability, wide dynamic range, bandwidth and especially robustness, it is necessary to design a feedback control loop, which must be robust, because the manufacturing process errors can be large. Especially, to obtain wide bandwidth, the feedback controller is indispensable, because the gyroscope is high Q factor system and has small open loop bandwidth. Moreover, the feedback controller reduces the effect...

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1131-1139
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• 1999

In this paper, we present a wide-bandwidth digital rebalance loop for a dynamically tuned gyroscope(DTG) based on {{{{ { H}_{2 } }}}} methodology. The operational principle and the importance of a rebalance loop are explaind, first. The augmented plant model is constructed, which includes a gyroscope model and an integrator. An {{{{ { H}_{ 2} }}}} based controller is designed for the augmented plant model. To verify the performance of the controller, a digital rebalance loop for a DTG is designed, fabricated and experimented. Through frequency response analyses and experiments using a real DTG, it is confirmed that the controller is more robustly stable and has a wider bandwidth compared with those of a conventional PID controller, contributing to the performance improvement of a DTG.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.