• KSII Transactions on Internet and Information Systems (TIIS)
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• v.2 no.2
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• pp.82-102
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• 2008

Packet losses tend to occur during short error bursts separated by long periods of relatively error-free transmission. There is also a significant spatial correlation in loss among the receiver nodes in a multicast session. To recover packet transmission errors at the transport layer, tree-based protocols construct a logical tree for error recovery before data transmission is started. The current tree construction scheme does not scale well because it overloads the sender node. We propose a scalable recovery tree construction scheme considering these properties. Unlike the existing tree construction schemes, our scheme distributes some tasks normally handled by the sender node to specific nodes acting as repair node distributors. It also allows receiver nodes to adaptively re-select their repair node when they experience unacceptable error recovery delay. Simulation results show that our scheme constructs the logical tree with reduced message and time overhead. Our analysis also indicates that it provides fast error recovery, since it can reduce the number of additional retransmissions from its upstream repair nodes or sender node.

• Journal of KIISE:Information Networking
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• v.31 no.2
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• pp.224-232
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• 2004

To guarantee the reliability in multicast transmission, researches providing reliability through hierarchical control tree which is independent on data channel tree are known to provide high scalability. However, the logical control tree in transport layer constructed without topology information of the corresponding network layer tree may inefficiently use the network resources because the logical control tree is not closely related to the tree topology of the network layer. A router assisted control tree mechanism presented in this paper would improve the efficiency of the link as well as it would remove the replicated data. In addition, it requires to a router a small change which examines the message type of the control tree.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.37-44
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• 2005

In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• The KIPS Transactions:PartC
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• v.18C no.6
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• pp.441-444
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• 2011

In this study, we present a method for efficiently aggregating network state information. It is especially useful for aggregating links that have both delay and bandwidth in an asymmetric network. Proposed method reduces the information distortion of logical link by integration process after similar measure and grouping of logical links in multi-level topology transformation to reduce the space complexity. It is applied to transform the full mesh topology whose Service Boundary Line (SBL) serves as its logical link into a spanning tree topology. Simulation results show that aggregated information accuracy and query response accuracy are higher than that of other known method.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.97-108
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• 2004

This paper proposes to use an algorithmic debugging technique for locating logical errors in Java programs. The algorithmic debugging is a semi-automated debugging technique that builds an execution tree from a source program and locates logical errors, if any, included in the program from the execution tree with top-down method. So, it is very important to build a suitable execution tree from the various programming languages. In this paper we propose the method for building an execution tree iron Java programs and walk through an example. This approach could reduce the number of interactions between a user and a debugging system than the traditional step-wise debugging technique.

• Management Science and Financial Engineering
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• v.12 no.2
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• pp.37-62
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• 2006

This paper considers the problem of designing logical tunnels in virtual private networks considering QoS guarantee which restricts the number of tunnel hops for each traffic routing. The previous researches focused on the design of logical tunnel itself and Steiner-tree based solution algorithms were proposed. However, we show that for some objective settings it is not sufficient and is necessary to consider both physical and logical connectivity at the same time. Thereupon, the concept of the layered network is applied to the logical tunnel design problem in virtual private networks. The layered network approach considers the design of logical tunnel as well as its physical routing and we propose a modified branch-and-price algorithm which is known to solve layered network design problems effectively. To show the performance of the proposed algorithm, computational experiments have been done and the results show that the proposed algorithm solves the given problem efficiently and effectively.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.345-348
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• 2003

Overlay multicast is proposed as an alternative approach for providing muticast services. A logical infrastructure is built to form an overlay network on top of the physical layer. In this paper, we propose an efficient overlay multicast in wireless ad hoc networks. The overlay multicast tree adapts to the changes in underlying networks. The multicast tree adjusted according to the local member information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.361-370
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• 2003

This paper attempts to improve the existing architecture of location register for location management in Private Network to Network Interface(PNNI)-based wireless ATM networks. Our approach enhances the hierarchical architecture of location registers based on a PNNI hierarchical architecture, which is referred to as the logical hierarchy architecture of location registers. This paper introduces a logical hierarchy architecture for location registers to reduce the cost of their location management. This logical hierarchy architecture of location registers begins with the lowest level physical location registers that are organized into clusters called logical groups. These logical groups are then represented in higher layers by logical nodes. These logical nodes are again grouped into clusters that are treated as single nodes by the next higher layer. In this way, all location registers are included in this tree-type logical hierarchy architecture. Compared with the existing physical hierarchy architecture of location registers, the analysis results show that the proposed logical hierarchy architecture can reduce the number of databases and thereby the average total location management cost.

• Journal of Information Processing Systems
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• v.20 no.2
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• pp.252-262
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• 2024

The multi-hop wireless sensor network (WSN) suffers from energy limitation and eavesdropping attacks. We propose a simple and energy-efficient convergecast mechanism using inter-flow random linear network coding that can provide confidentiality to the multi-hop WSN. Our scheme consists of two steps, constructing a logical tree of sensor nodes rooted at the sink node, with using the Bloom filter, and transmitting sensory data encoded by sensor nodes along the logical tree upward to the sink where the encoded data are decoded according to our proposed multi-hop network coding (MHNC) mechanism. We conducted simulations using OMNET++ CASTALIA-3.3 framework and validated that MHNC outperforms the conventional mechanism in terms of packet delivery ratio, data delivery time and energy efficiency.