• Nuclear Engineering and Technology
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• 제41권10호
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• pp.1223-1234
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• 2009

The outlines of seismic PSA implementation standards and seismic hazard evaluation procedure were shown. An overview of the cause investigation of seismic motion amplification on the Niigata-ken Chuetsu-oki (NCO) earthquake was also shown. Then, the contents for improving the seismic hazard evaluation methodology based on the lessons learned from the NCO earthquake were described. (1) It is very important to recognize the effectiveness of a fault model on the detail seismic hazard evaluation for the near seismic source through the cause investigation of the NCO earthquake. (2) In order to perform and proceed with a seismic hazard evaluation, the Japan Nuclear Energy Safety Organization has proposed the framework of the open deliberation rule regarding the treatment of uncertainty which was made so as to be able to utilize a logic tree. (3) The b-value evaluation on the "Stress concentrating zone," which is a high seismic activity around the NCO hypocenter area, should be modified based on the Gutenberg-Richter equation.

• ETRI Journal
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• 제37권3호
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• pp.584-594
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• 2015

To date, many different kinds of logic styles for hardware countermeasures have been developed; for example, SABL, TDPL, and DyCML. Current mode-based logic styles are useful as they consume less power compared to voltage mode-based logic styles such as SABL and TDPL. Although we developed TPDyCML in 2012 and presented it at the WISA 2012 conference, we have further optimized it in this paper using a binary decision diagram algorithm and confirmed its properties through a practical implementation of the AES S-box. In this paper, we will explain the outcome of HSPICE simulations, which included correlation power attacks, on AES S-boxes configured using a compact NMOS tree constructed from either SABL, CMOS, TDPL, DyCML, or TPDyCML. In addition, to compare the performance of each logic style in greater detail, we will carry out a mutual information analysis (MIA). Our results confirm that our logic style has good properties as a hardware countermeasure and 15% less information leakage than those secure logic styles used in our MIA.

• 한국가스학회:학술대회논문집
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• 한국가스학회 1999년도 추계학술발표회 논문집
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• pp.244-249
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• 1999

• 한국철도학회논문집
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• 제9권6호
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• pp.725-731
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• 2006

Hot Standby sparing system detecting faults by using software, and being tolerant any faults by using Hardware Redundancy is difficult to perform quantitative reliability prediction and to detect real time faults. Therefore, this paper designs Hot Standby sparing system using hardware basis self checking logic in order to overcome this problem. It also performs failure mode analysis of Hot Standby sparing system with designed self checking logic by using FMEA (Failure Mode Effect Analysis), and identifies reliability assessment of the controller designed by quantifying the numbers of failure development by using FTA (Fault Tree Analysis)

• 한국언어정보학회:학술대회논문집
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• 한국언어정보학회 2007년도 정기학술대회
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• pp.42-53
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• 2007

Looking back the history of formal treatment of linguistics, we cannot disregard the contribution of possible world semantics. Intensional logic of Montague semantics, DRT (Discourse Representation Theory), mental space, and situation theory are closely related to or compared with the notion of possible world. All these theories have commonly clarified the structure of belief context or uncertain knowledge, employing hypothesized worlds. In this talk, I firstly brief the pedigree of these theories. Next, I will introduce the recent development of modal logic for the representation of (i) knowledge and belief and (ii) time, in which belief modality is precisely discussed together with the accessibility among possible worlds. I will refer to BDI (belief-desire-intention) logic, CTL (computational tree logic), and sphere-based model in belief revision. Finally, I will discuss how these theories could be applied to the further development of analyses of natural language.

• 대한산업공학회지
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• 제20권3호
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• pp.125-137
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• 1994

Manufacturing environs constantly change, and any efficient software system to be used in manufacturing must be able to adapt to the varying situations. In a CAPP (Computer-Aided Process Planning) system, a learning capability is necessary for the CAPP system to do change along with the manufacturing system. Unfortunately only a few CAPP systems currently possess learning capabilities. This research aims at the development of a learning system which can increase the knowledge in a CAPP system. A part in the system is represented by frames and described interactively. The process information and process planning logic is represented using a decision tree. The knowledge expansion is carried out through an interactive expansion of the decision tree according to human advice. Algorithms for decision tree modification are developed. A path can be recommended for an unknown part of limited scope. The processes are selected according to the criterion such as minimum time or minimum cost. The decision tree, and the process planning and learning procedures are formally defined.

• Journal of Construction Engineering and Project Management
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• 제8권4호
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• pp.1-24
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• 2018

In the last decade, the use of Building Information Modeling (BIM) as a new technology has been applied with traditional Computer-aided design implementations in an increasing number of architecture, engineering, and construction projects and applications. Its employment alongside construction management, can be a valuable tool in helping move these activities and projects forward in a more efficient and time-effective manner. The traditional stakeholders, i.e., Owner, A/E and the Contractor are involved in this BIM system that is used in almost every activity of construction projects, such as design, cost estimate and scheduling. This article extracts major features of the application of BIM from perspective of participating BIM components, along with the different phrases, and applies to them a logistic analysis using a fuzzy performance tree, quantifying these phrases to judge the effectiveness of the BIM techniques employed. That is to say, these fuzzy performance trees with fuzzy logic concepts can properly translate the linguistic rating into numeric expressions, and are thus employed in evaluating the influence of BIM applications as a mathematical process. The rotational fuzzy models are used to represent the membership functions of the performance values and their corresponding weights. Illustrations of the use of this fuzzy BIM performance tree are presented in the study for the uninitiated users. The results of these processes are an evaluation of BIM project performance as highly positive. The quantification of the performance ratings for the individual factors is a significant contributor to this assessment, capable of parsing vernacular language into numerical data for a more accurate and precise use in performance analysis. It is hoped that fuzzy performance trees and fuzzy set analysis can be used as a tool for the quality and risk analysis for other construction techniques in the future. Baldwin's rotational models are used to represent the membership functions of the fuzzy sets. Three scenarios are presented using fuzzy MEAN, AND and OR gates from the lowest to intermediate levels of the tree, and fuzzy SUM gate to relate the intermediate level to the top component of the tree, i.e., BIM application final performance. The use of fuzzy MEAN for lower levels and fuzzy SUM gates to reach the top level suggests the most realistic and accurate results. The methodology (fuzzy performance tree) described in this paper is appropriate to implement in today's construction industry when limited objective data is presented and it is heavily relied on experts' subjective judgment.

• 대한전자공학회논문지SD
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• 제40권6호
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• pp.447-458
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• 2003

고속동작을 하는 곱셈기는 DSP의 기본 블록 설계에 있어서 필수적이다. 전형적으로 신호처리분야에 있어서 반복 알고리듬은 다량의 곱셈연산을 필요로 하고, 이 곱셈연산을 첨가하고 실행하는데 사용된다. 본 논문은 32×32-b RST를 적용한 병렬 구조 곱셈기의 매크로 블록을 제시한다. Tree part의 속도를 향상시키기 위해 변형된 부분곱 발생 방법이 구조레벨에서 고안되었다. 이것은 4 레벨을 압축된 3 레벨로 줄였고, 4-2 압축기를 사용한 월리스 트리 구조에서도 지연시간을 감소시켰다. 또한, tree part가 CSA tree를 생성하기 위한 4개의 모듈러 블록과 결합이 되게 하였다. 그러므로 곱셈기 구조는 부스 셀렉터, 압축기, 새로운 부분곱 발생기(MPPG : Modified Partial Product Generator)로 구성된 같은 모듈에 규칙적으로 레이아웃 될 수 있다. 회로레벨에서 적은 트랜지스터 수와 엔코더로 구성된 새로운 부스 셀렉터가 제안되었다. 부스셀렉터에서의 트랜지스터 수의 감소는 전체 트랜지스터 수에 큰 영향을 끼친다. 설계된 셀렉터에는 9개의 PTL(Pass Transistor Logic)을 사용한다. 이것은 일반적인 트랜지스터 수의 감소와 비교했을 때 50% 줄인 것이다. 단일폴리, 5중금속, 2.5V, 0.25㎛ CMOS공정을 사용하여 설계하고, Hspice와 Epic으로 검증하였다. 지연시간은 4.2㎱, 평균 전력소모는1.81㎽/㎒이다. 이 결과들은 발표된 성능이 우수한 일반적인 곱셈기보다도 성능이 우수하다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1993년도 춘계학술대회 논문집
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• pp.305-309
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• 1993

The application of fault tree technique to the analysis of compressor failure is considered. The techniques involve the decomposition of the system into a logic diagram or fault tree in whichcertain basic or primary events lead to a specified top event which signifiss the total failure of the system. The fault trees are used to obtain miniumal cut sets from whichthe modes of system failure and, hence the reliability for the top event can be calculated. The method of constructing fault trees and the subsequent estimation of reliability of the system is illustrated through a compressor failure. FTA is roved to be efficient to investigate the compressor fault train.

• 한국시뮬레이션학회논문지
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• 제4권2호
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• pp.61-68
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• 1995

The performance of event-driven logic simulation frequently used for VLSI design verification depends on the data structures for event queues. This paper improves the existing Timing Wheel as a data structure for an event queue. In case of the use of B+ tree, an efficient node degree is also presented based on the experiment results. A new Timing Wheel index structure, which eliminates the insertion and deletion overhead of B+ tree, is proposed and analyzed.