• 제어로봇시스템학회논문지
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• 제12권8호
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• pp.834-841
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• 2006

Recently, many enterprises are installing AMSs(Automated Manufacturing Systems) for their competitive advantages. As the level of automation increases, proper design and validation of control logic is a imperative task for the successful operation of AMSs. However, current discrete event simulation methods mainly focus on the performance evaluation. As a result, they lack the modeling capabilities for the detail logic of automated manufacturing system controller. Proposed in this paper is a method of validation of the controller logic for automated material handling system using an object-oriented design and simulation. Using this method, FA engineers can validate the controller logic easily in earlier stage of system design, so they can reduce the time for correcting the logic errors and enhance the productivity of control program development Generated simulation model can also be used as a communication tool among FA engineers who have different experiences and disciplines.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권1호
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.107-114
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• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• 전자공학회논문지A
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• 제33A권5호
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.579-581
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• 1988

This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.

• Journal of Information Display
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• 제6권1호
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.1103-1106
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• 1996

Disturbance Accommodating Attitude control logic for 3-axis stabilized spacecraft is designed and compared with PIID control logic. PID controller provide the zero steady error for constant disturbances. PIID controller detect and cancel disturbances upto the ramp input. PID control logic is designed as the main control logic. We designed the disturbance observer to detect the effect of disturbance using the sinusoidal function. The detected disturbance are compensated by the additional control logic. The comparison simulation is conducted between PIID and PIID with DAC. The simulation results show that PIID with DAC shows the better attitude pointing accuracy.

• 한국태양에너지학회 논문집
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• 제32권4호
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• pp.96-102
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• 2012

The minimum airflow of VAV terminal boxes is a key factor for comfort, indoor air quality(IAQ) and energy cost. If the minimum airflow is not reasonable, it would waste energy and make IAQ problems. There are two types of VAV terminal box control logic. One is the single maximum, another is the dual maximum control logic. Dual maximum control logic is more efficiency way to reduce the energy consumption. It has a minimum airflow set point and a heating maximum set point. It allows the minimum airflow set point to be much lower than single maximum control logic. A building simulation was conducted to evaluate the energy consumption and the IAQ according to the control logic of the V AV terminal box. In the simulation, dual maximum control logic can save the energy up to 6.5% compared to the single maximum control logic.

• 한국시뮬레이션학회논문지
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• 제17권3호
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• pp.9-18
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• 2008

단순히 퍼지만을 사용하여 시스템을 연동하는 경우와 퍼지로직을 같이 사용하여 침입 탐지 에이전트의 시스템 성능을 향상시키는 경우에 관한 연구로서, 블랙보드 기반의 비퍼지로직을 사용하는 경우와 블랙보드 기반의 퍼지 로직을 사용하는 경우을 비교한다. 또한 BBA를 통해 정적으로 대응하던 시스템을 향상시켜 동적 대응이 가능하게 구성하여 현실적인 시스템이 되도록 구성하였다. 대상 시스템의 성능을 평가하기 위하여 시뮬레이션을 수행하였다. 퍼지 시스템을 사용함으로써 false negative를 줄일 수 있었다. 분산 침입탐지를 위해 포함된 퍼지로직은 다양한 요소를 고려하기 때문에 침입의 성능을 높일 수 있다. 퍼지시스템을 사용하는 경우와 비 퍼지 시스템의 성능을 비교함으로써 퍼지 시스템의 성능 향상을 보이며, 이러한 비교를 통해 전체 시스템의 성능 향상을 보인다.

• Smart Structures and Systems
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• 제14권6호
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.