• Title/Summary/Keyword: logic sharing

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The Effect of Security Information Sharing and Disruptive Technology on Patient Dissatisfaction in Saudi Health Care Services During Covid-19 Pandemic

  • Beyari, Hasan;Hejazi, Mohammed;Alrusaini, Othman
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.16 no.10
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    • pp.3313-3332
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    • 2022
  • This study is an investigation into the factors affecting patient dissatisfaction among Saudi hospitals. The selected factors considered for analysis are security of information sharing, operational practices, disruptive technologies, and the ease of use of EHR patient information management systems. From the literature review section, it was clear that hardly any other studies have embraced these concepts in one as was intended by this study. The theories that the study heavily draws from are the service dominant logic and the feature integration theory. The study surveyed 350 respondents from three large major hospitals in three different metropolitan cities in the Kingdom of Saudi Arabia. This sample came from members of the three hospitals that were willing to participate in the study. The number 350 represents those that successfully completed the online questionnaire or the limited physical questionnaires in time. The study employed the structural equation modelling technique to analyze the associations. Findings suggested that security of information sharing had a significant direct effect on patient satisfaction. Operational practice positively mediated the effect of security of information sharing on patient dissatisfaction. However, ease of use failed to significant impact this association. The study concluded that to improve patient satisfaction, Saudi hospitals must work on their systems to reinforce them against the active threats on the privacy of patients' data by leveraging disruptive technology. They should also improve their operational practices by embracing quality management techniques relevant to the healthcare sector.

Verification and Implementation of a Service Bundle Authentication Mechanism in the OSGi Service Platform Environment (OSGi 서비스 플랫폼 환경에서 서비스 번들 인증 메커니즘의 검증 및 구현)

  • 김영갑;문창주;박대하;백두권
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.27-40
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    • 2004
  • The OSGi service platform has several characteristics as in the followings. First, the service is deployed in the form of self-installable component called service bundle. Second, the service is dynamic according to its life-cycle and has interactions with other services. Third, the system resources of a home gateway are restricted. Due to these characteristics of a home gateway, there are a lot of rooms for malicious services can be Installed, and further, the nature of service can be changed. It is possible for those service bundles to influence badly on service gateways and users. However, there is no service bundle authentication mechanism considering those characteristics for the home gateway In this paper, we propose a service bundle authentication mechanism considering those characteristics for the home gateway environment. We design the mechanism for sharing a key which transports a service bundle safely in bootstrapping step that recognize and initialize equipments. And we propose the service bundle authentication mechanism based on MAC that use a shared secret created in bootstrapping step. Also we verify the safety of key sharing mechanism and service bundle authentication mechanism using a BAN Logic. This service bundle authentication mechanism Is more efficient than PKI-based service bundle authentication mechanism or RSH protocol in the service platform which has restricted resources such as storage spaces and operations.

Low Complexity Gradient Magnitude Calculator Hardware Architecture Using Characteristic Analysis of Projection Vector and Hardware Resource Sharing (정사영 벡터의 특징 분석 및 하드웨어 자원 공유기법을 이용한 저면적 Gradient Magnitude 연산 하드웨어 구현)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.4
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    • pp.414-418
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    • 2016
  • In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

Development of Asynchronous Blocking Algorithm through Asynchronous Case Study of Steam Turbine Generator (스팀터빈 발전기 비동기 투입 사례연구를 통한 비동기 방지 알고리즘 개발)

  • Lee, Jong-Hweon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.10
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    • pp.1542-1547
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    • 2012
  • Asynchronous phenomenon occurs on the synchronous generators under power system when a generator's amplitude of electromagnetic force, phase angle, frequency and waveform etc become different from those of other synchronous generators which can follow instantly varying speed of turbine. Because the amplitude of electromagnetic force, phase frequency and waveform differ from those of other generators with which are to be put into parallel operation due to the change of excitation condition for load sharing and the sharing load change, if reactive current in the internal circuit circulates among generators, the efficiency varies and the stator winding of generators are overheated by resistance loss. When calculation method of protection settings and logic for protection of generator asynchronization will be recommended, a distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome asynchronizing protection, this paper describes an improved backup protection coordination scheme using a new logic that will be suggested.

A Study on Protection of Generator Asynchronization by Impedance Relaying (임피던스 계전기를 이용한 발전기 비동기 투입 보호 연구)

  • Lee, Jong-Hweon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.11
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    • pp.2000-2006
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    • 2011
  • Asynchronous phenomenon occurs on the synchronous generators under power system when a generator's amplitude of electromagnetic force, phase angle, frequency and waveform etc become different from those of other synchronous generators which can follow instantly varying speed of turbine. Because the amplitude of electromagnetic force, phase frequency and waveform differ from those of other generators with which are to be put into parallel operation due to the change of excitation condition for load sharing and the sharing load change, if reactive current in the internal circuit circulates among generators, the efficiency varies and the stator winding of generators are overheated by resistance loss. Where calculation method of protection settings and Logic for Protection of Generator Asynchronization will be recommended, A distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, Zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome asynchronizing protection this paper describes an improved backup protection coordination scheme using a new Logic that will be suggested.

PROMISE: A QR Code PROjection Matrix Based Framework for Information Hiding Using Image SEgmentation

  • Yixiang Fang;Kai Tu;Kai Wu;Yi Peng;Yunqing Shi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.17 no.2
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    • pp.471-485
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    • 2023
  • As data sharing increases explosively, such information encoded in QR code is completely public as private messages are not securely protected. This paper proposes a new 'PROMISE' framework for hiding information based on the QR code projection matrix by using image segmentation without modifying the essential QR code characteristics. Projection matrix mapping, matrix scrambling, fusion image segmentation and steganography with SEL(secret embedding logic) are part of the PROMISE framework. The QR code could be mapped to determine the segmentation site of the fusion image as a binary information matrix. To further protect the site information, matrix scrambling could be adopted after the mapping phase. Image segmentation is then performed on the fusion image and the SEL module is applied to embed the secret message into the fusion image. Matrix transformation and SEL parameters should be uploaded to the server as the secret key for authorized users to decode the private message. And it was possible to further obtain the private message hidden by the framework we proposed. Experimental findings show that when compared to some traditional information hiding methods, better anti-detection performance, greater secret key space and lower complexity could be obtained in our work.

Optimization of Pipelined Discrete Wavelet Packet Transform Based on an Efficient Transpose Form and an Advanced Functional Sharing Technique

  • Nguyen, Hung-Ngoc;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of Information Processing Systems
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    • v.15 no.2
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    • pp.374-385
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    • 2019
  • This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

An Emulation System for Efficient Verification of ASIC Design (ASIC 설계의 효과적인 검증을 위한 에뮬레이션 시스템)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.17-28
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    • 1999
  • In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

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Development of 8kW ZVZCS Full Bridge DC-DC Converter by Parallel Operation (병렬제어를 적용한 8kW급 영전압/영전류 풀 브릿지 DC-DC 컨버터 개발)

  • Rho, Min-Sik
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.5
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    • pp.400-408
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    • 2007
  • In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

A Study on the Measurement of Force Improvement Effectiveness of Korean Joint Command & Control System (한국군합동지휘통제체계의 전투력 상승효과 측정에 관한 연구)

  • Jung, Whan-Sik;Lee, Jae-Young
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2008.10a
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    • pp.348-352
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    • 2008
  • KJCCS(Korean Joint Command & Control System) is a system that integrate each military tactics C4ISR into JCS(Joint Chiefs of Staff) level. It is established in major CP(Commanding Post) and provides all battlefield situation in real time by sharing that between connection troops. The objective of this study is to suggest a way for the measurement of force improvement effectiveness of KJCCS. C2 model is applied to measure force improvement effectiveness of KJCCS. This study will be also present a requirement logic for C4ISR system acquisition later.

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