• Journal of Information Display
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• 제6권1호
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• Journal of the Optical Society of Korea
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• 제16권4호
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• pp.432-442
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• 2012

In this paper, we propose, analyze and simulate the performances of some new plasmonic logic gates in two dimensional plasmonic waveguides with nanodisk resonators, using the numerical method of finite difference time domain (FDTD). These gates, including XOR, XNOR, NAND, and NOT, can provide the highly integrated optical logic circuits. Also, by cascading and combining these basic logic gates, any logic operation can be realized. These devices can be utilized significantly in optical processing and telecommunication devices.

• 전기전자학회논문지
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• 제8권1호
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• pp.47-53
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• 2004

본 논문에서는 3치 논리 게이트를 바탕으로 하는 3치 데이터 처리를 위한 3치 flip-flop을 설계하였다. 제안한 flip-flop들은 3치 전압 모드 NMAX, NMIN, INVERTER 게이트를 사용하여 설계하였다. 또한 CMOS 기술을 사용하였고 다른 게이트들 보다 낮은 공급 전압과 낮은 전력소모 특성을 포함하고 있다. 제안한 회로는 0.35um 표준 CMOS 공정에서 설계되었고 3.3v의 공급 전압원을 사용하였다. 제안된 3치 flip-flop 구조는 3치 논리 게이트를 사용하여 VLSI 구현에 적합하고 높은 모듈성의 장점을 갖고 있다.

• 전자공학회논문지A
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• 제31A권2호
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• pp.75-80
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• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• Nuclear Engineering and Technology
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• 제53권4호
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• pp.1146-1156
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• 2021

Single-unit probabilistic safety assessment (SUPSA) has complex Boolean logic equations for accident sequences. Multi-unit probabilistic safety assessment (MUPSA) model is developed by revising and combining SUPSA models in order to reflect plant state combinations (PSCs). These PSCs represent combinations of core damage and non-core damage states of nuclear power plants (NPPs). Since all these Boolean logic equations have complemented gates (not gates), it is not easy to generate exact Boolean solutions. Delete-term approximation method (DTAM) has been widely applied for generating approximate minimal cut sets (MCSs) from the complex Boolean logic equations with complemented gates. By applying DTAM, approximate conditional core damage probability (CCDP) has been calculated in SUPSA and MUPSA. It was found that CCDP calculated by DTAM was overestimated when complemented gates have non-rare events. Especially, the CCDP overestimation drastically increases if seismic SUPSA or MUPSA has complemented gates with many non-rare events. The objective of this study is to suggest a new quantification method named probability subtraction method (PSM) that replaces DTAM. The PSM calculates accurate CCDP even when SUPSA or MUPSA has complemented gates with many non-rare events. In this paper, the PSM is explained, and the accuracy of the PSM is validated by its applications to a few MUPSAs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 대한전자공학회논문지SD
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• 제44권9호
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• pp.54-58
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• 2007

LTPS TFT의 개발과 성능 향상은 패널에 다양한 디지털 회로를 내장하는 SOP의 비약적 발전에 기여하였다. 본 논문에서는 일반적으로 적용되는 낮은 성능의 CMOS 논리게이트를 대체할 수 있는 전류모드 논리(CML) 게이트의 설계 방법을 소개한다. CML 인버터는 낮은 로직스윙, 빠른 응답 특성을 갖도록 설계할 수 있음을 보였으며 높은 소비전력의 단점도 동작 속도가 높아질수록 CMOS의 경우와 근사해졌다. 아울러 전류 구동능력을 키울 필요가 없는 까닭에 많은 수의 소자가 사용되지만 면적은 오히려 감소하는 것을 확인하였다. 특히 비반전 및 반전 출력이 동시에 생성되므로 noise immunity가 우수하다. 다수 입력을 갖는 NAND/AND 및 NOR/OR 게이트는 같은 회로에 입력신호를 바꾸어 구현할 수 있고 MUX와 XNOR/XOR 게이트도 같은 회로를 사용하여 구현할 수 있음을 보였다. 결론적으로 CML 게이트는 다양한 함수를 단순한 몇가지의 회로로 구성할 수 있으며 낮은 소비전력, 적은 면적, 개선된 동작속도 등을 동시에 추구할 수 있는 대안임을 확인하였다.

• 한국통신학회논문지
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• 제21권11호
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• pp.2978-2990
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• 1996

With the advent of multimedia era, there are ever increasing interest in computer music and sound syntheis. An FM type sound synthesizing method makes possible the syntheis ofvarious sounds ofmusical instruments with a relatively simple hardware architecture. Therefore, in this paper, we designed a hardware architecture for real-time sound synthesizer and its logic gates. In this paper, we designed a basic sound generator for implementation of real-time logic gates, analzed characteristics of sounds synthesized in this architecture and extracted parameters of FM sounds of musical instruments by using the Csound software. The major bolkcs to build the hardware are a phase-generator, a singe-function-generator, an envelope-generator and a multiplier-part. Finally, logic circuits are designed and verified in VHDL and logic gates by 1.0um standard cell library, which will be easily implementable by the form of ASIC.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2006년도 하계학술대회
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• pp.19-23
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• 2006

Latching optical switches and optical logic gates AND and OR are demonstrated, for the first time, by the monolithic integration of a vertical cavity lasers with depleted optical thyristor structure, which have not only a low threshold current with 0.65 mA. but also a high on/off contrast ratio more than 50 dB. By simple operating technique with changing a reference switching voltage, this single device operates as two logic functions, optical logic AND and OR. The thyristor laser fabricated using the oxidation process achieved a high optical output power efficiency and a high sensitivity to the optical input light.

• 한국광학회지
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• 제13권5호
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• pp.414-420
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• 2002

본 연구에서는 bacteriorhodopsin(bR)이 첨가된 고분자 박막을 이용하여 광 논리회로 특성을 구현하였다. bR은 분광학적으로 구분되는 몇 단계의 중간단계로 구성된 복잡한 참순환 과정을 수반하고 있다. 우리는 bR의 광순환 과정중 B상태와 M상태의 흡수도 변화를 고려하여 He-Ne 레이저(632.8 nm)와 He-Cd 레이저(413 nm) 이용하여 광학적 논리회로를 구현하였다. 또한 B상태와 K상태간의 흡수 스펙트럼을 고려하여 He-Ne 레이저(632.8 nm)와 Nd-YAG 레이저의 제2고조파인 532 nm를 이용하여 고속 AND logic gate를 구현하였다.