• Title/Summary/Keyword: locking time

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A Reference Spur Suppressed PLL with Two-Symmetrical Loops (기준 신호 스퍼의 크기를 줄인 두 개의 대칭 루프를 가진 위상고정루프)

  • Choi, Hyun-Woo;Choi, Young-Shig
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.5
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    • pp.99-105
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    • 2014
  • A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

Design of a tracking and demodulation circuit for wideband DDMA in IMT-2000 (IMT-2000 광대역 CDMA의 동기추적 및 데이터 복조 회로구현)

  • 권형철;오현서;이재호;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.6A
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    • pp.871-880
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    • 1999
  • In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

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The Relationship between Temporomandibular Disorders(TMD) and Occlusion (측두하악장애와 교합요인의 관계)

  • Kim, Seong-Taek;Lee, You-Sik
    • Journal of Dental Rehabilitation and Applied Science
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    • v.21 no.1
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    • pp.43-57
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    • 2005
  • Temporomandibular disorders have been defined as a collective term embracing a number of clinical problems that involve the temporomandibular joint, the masticatory nuscles, and associated structures. There have been many different contributing factors of TMDs which were traumatic, occlusal, pathophysiological and psychosocial. Among there factors, the effect of occlusion on TMDs have been a controversy for a long time. The purpose of this study was to investigate the effect of occlusal factors and oral habits on TMDs. In this study, 140 subjects with signs and symptoms of TMDs and diagnosed of TMD in the Orofacial Pain clinic of Yonsei University Dental Hospital though March to July 2004 were selected for the TMDs group and 50 subjects without any signs and symptoms of TMDs as the control group. The subjects were evaluated clinically in TMDs' Occlusal and Prosthodontic Restoration examinations. TMDs' examination was composed of the TMJ pain, sound, locking, temporal or masseter muscle palpation, mandibular movement, oral habits and headache. Occlusal examination was made of overjet, overbite, lost teeth number, nonfunctional interference, midline shift, then pattern of lateral movement and attrition. prosthodontic restoration examination had the existence of restoration, placement, then number of crown or bridge and Satisfiable index which estimated the quality of occlusal state of prosthodontic restorations. Following results were obtained : 1. The prevalence of TMDs was higher in their 20s & 30s, female of the TMD patients group. 2. The clenching frequency in the TMDs group(40.71%) was higher than those in the control group(18.00%), and there was a significant statistical difference(p<0.05). 3. The frequency of Nonfunctional interference in the TMDs group(10.00%) was higher than those in then Control group(2.00%), and there was a significant statistical difference(p<0.05). The result of this study indicated TMDs prevalence was higher in their 20s, 30s, female group of TMDs patients similar to the previous studies. Clenching and nonfunctional interference were estimated as the contributing factors of TMDs.

A Novel Carrier-to-noise Power Ratio Estimation Scheme with Low Complexity for GNSS Receivers (GNSS 수신기를 위한 낮은 복잡도를 갖는 새로운 반송파 대 잡음 전력비 추정기법)

  • Yoo, Seungsoo;Baek, Jeehyeon;Yeom, Dong-Jin;Jee, Gyu-In;Kim, Sun Yong
    • Journal of Institute of Control, Robotics and Systems
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    • v.20 no.7
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    • pp.767-773
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    • 2014
  • The carrier-to-noise power ratio is a key parameter for determining the reliability of PVT (Position, Velocity, and Time) solutions which are obtained by a GNSS (Global Navigation Satellite System) receiver. It is also used for locking a tracking loop, deciding the re-acquisition process, and processing advanced navigation in the receiver subsystem. The representative carrier-to-noise power ratio estimation schemes are the narrowband-wideband power ratio method (NW), the MM (Moment Method), and Beaulieu's method (BL). The NW scheme is the most classical one for commercial GNSS receivers. It is often used as an authoritative benchmark for assessing carrier-to-noise power estimation schemes. The MM scheme is the least biased solution among them, and the BL scheme is a simpler scheme than the MM scheme. This paper focuses on the less biased estimation with low complexity when the residual phase noise remains, then proposes a novel carrier-to-noise power ratio estimation scheme with low complexity for GNSS receivers. The asymptotic bias of the proposed scheme is derived and compared with others, and the simulation results demonstrate that the complexity of the proposed scheme is lowest among them, while the estimation performance of the proposed scheme is similar to those of the BL and MM schemes in normal and high gained reception environments.

Development of High Spectral Resolution Lidar System for Measuring Aerosol and Cloud

  • Zhao, Ming;Xie, Chen-Bo;Zhong, Zhi-Qing;Wang, Bang-Xin;Wang, Zhen-Zhu;Dai, Pang-Da;Shang, Zhen;Tan, Min;Liu, Dong;Wang, Ying-Jian
    • Journal of the Optical Society of Korea
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    • v.19 no.6
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    • pp.695-699
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    • 2015
  • A high spectral resolution lidar (HSRL) system based on injection-seeded Nd:YAG laser and iodine absorption filter has been developed for the quantitative measurement of aerosol and cloud. The laser frequency is stabilized at 80 MHz by a frequency locking system and the absorption line of iodine cell is selected at the 1111 line with 2 GHz width. The observations show that the HSRL can provide vertical profiles of particle extinction coefficient, backscattering coefficient and lidar ratio for cloud and aerosol up to 12 km altitude, simultaneously. For the measured cases, the lidar ratios are 10~20 sr for cloud, 28~37 sr for dust, and 58~70 sr for urban pollution aerosol. It reveals the potential of HSRL to distinguish the type of aerosol and cloud. Time series measurements are given and demonstrate that the HSRL has ability to continuously observe the aerosol and cloud for day and night.

Design Methodology of the Frequency-Adaptive Negative-Delay Circuit (주파수 적응성을 갖는 부지연 회로의 설계기법)

  • Kim, Dae-Jeong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.37 no.3
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    • pp.44-54
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    • 2000
  • In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

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Design of a 5.2GHz/2.4GHz Dual band CMOS Frequency Synthesizer for WLAN (WLAN을 위한 5.2GHz/2.4GHz 이중대역 주차수 합성기의 설계)

  • Kim, Kwang-Il;Lee, Sang-Cheol;Yoon, Kwang-Sub;Kim, Seok-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.1A
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    • pp.134-141
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    • 2007
  • This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

An Extremely Small Size Multi-Loop Phase Locked Loop (복수개의 부궤환 루프를 가진 초소형 크기의 위상고정루프)

  • Choi, Young-Shig;Han, Geun-Hyeong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.1
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    • pp.1-6
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    • 2019
  • An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

Design of HUST-PTF beamline control system for fast energy changing

  • Li, Peilun;Li, Dong;Qin, Bin;Zhou, Chong;Han, Wenjie;Liao, Yicheng;Chen, Aote
    • Nuclear Engineering and Technology
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    • v.54 no.8
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    • pp.2852-2858
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    • 2022
  • A proton therapy facility is under development at Huazhong University of Science and Technology (HUST). To meet the need for fast energy changes during treatments, a beamline control system (BCS) has been designed and implemented. The BCS coordinates and controls various beamline devices by adopting a distributed architecture divided into three layers: the client, server, and device layers. Among these, the design of the server layer is the key to realize fast energy changes. The server layer adopts the submodule programming paradigm and optimizes the data interface among modules, allowing the main workflow to be separated from the device workflow and data. Furthermore, this layer uses asynchronous, multithreaded, and thread-locking methods to improve the system's ability to operation efficiently and securely. Notably, to evaluate the changing energy status over time, a dynamic node update method is adopted, which can dynamically adjust the update frequency of variable nodes. This method not only meets the demand for fast updates on energy changes but also reduces the server's communication load in the steady state. This method is tested on a virtual platform, and the results are as expected.

A modified method of augmented distal clavicle fracture osteosynthesis with a Fibertape coracoclavicular cerclage

  • Wu, ChengHan;Teo, Timothy Wei Wen;Wee, Andy Teck Huat;Toon, Dong Hao
    • Clinics in Shoulder and Elbow
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    • v.25 no.3
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    • pp.230-235
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    • 2022
  • Background: Unstable distal clavicles experience high non-union rates, prompting surgeons to recommend surgery for more predictable outcomes. There is a lack of consensus on the optimal method of surgical fixation, with an array of techniques described in the literature. We describe an alternative method of fixation involving the use of a distal clavicular anatomical locking plate with Fibertape cerclage augmentation in our series of patients. Methods: Nine patients (8 males and 1 female), with a mean age of 36 years, who sustained unstable fracture of the distal clavicle in our institution were treated with our described technique. Postoperative range of motion, functional and pain scores, and time to radiographic union were measured over a mean follow-up period of 10 months. Incidences of postoperative complications were also recorded. Results: At the last patient consult, the mean visual analog scale score was 0.88±0.35, with a mean Disabilities of the Arm, Shoulder, and Hand (DASH) score of 1.46±0.87 and American Shoulder and Elbow Surgeons (ASES) score of 94.1±3.57. The mean range of motion achieved was forward flexion at 173°±10.6°, abduction at 173°±10.6°, and external rotation at 74.4°±10.5°. All patients achieved internal rotation at a vertebral height of at least L2 with radiographical union at a mean of 10 weeks. No removal of implants was required. Conclusions: Our described technique of augmented fixation of the distal clavicle is effective, produces good clinical outcomes, and has minimal complications.